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I am trying to synthesize my Verilog code, which I wrote using Modelsim tool for 8-bit MAC in Cadence Encounter. The file that is generated after synthesis has to be re-checked for functionality in Modelsim. However, this time it is generating many errors of the form:

    ** Error: /ugassignments/ma3ps139/cadence/vedic8_syn/synthesis/fsd0k_a_generic_core_21.lib.src(21703): $width( posedge CK:350 ps, :400 ps, 159 ps ); 

Also, the synthesized code file shows to have many "UNCONNECTED" wires, which is why it is not generating the results. However, when I try to trace back that part of the synthesized code to the original code, no such dangling wires seem to be there.

I am new to this. Please help.

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  • \$\begingroup\$ Please share your RTL code for the UNCONNECTED wires issue. \$\endgroup\$ – Greg May 8 '14 at 18:59
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According to the error message, your clock is high for only 350 ps and is required to be high for 400 ps. Could be you need to run a slower clock or adjust the duty cycle.

You'll need to post more info for the many "UNCONNECTED" wires issue.

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