I am trying to synthesize my Verilog code, which I wrote using Modelsim tool for 8-bit MAC in Cadence Encounter. The file that is generated after synthesis has to be re-checked for functionality in Modelsim. However, this time it is generating many errors of the form:
** Error: /ugassignments/ma3ps139/cadence/vedic8_syn/synthesis/fsd0k_a_generic_core_21.lib.src(21703): $width( posedge CK:350 ps, :400 ps, 159 ps );
Also, the synthesized code file shows to have many "UNCONNECTED" wires, which is why it is not generating the results. However, when I try to trace back that part of the synthesized code to the original code, no such dangling wires seem to be there.
I am new to this. Please help.