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I thinking of using Cyclone V FPGA and its hardware memory controller:

There is "Cyclone V FPGA Multiport Memory Controller" document from Altera:

http://www.altera.com/devices/fpga/cyclone-v-fpgas/overview/memory-controller/cyv-memory.html

Configurable memory width of 8, 16, 24, 32, and 40 bits

The PDF "External Memory Interfaces in Cyclone V Devices" has more details http://www.altera.com/literature/hb/cyclone-v/cv_52006.pdf

Hard Memory Controller

The Cyclone V devices feature dedicated hard memory controllers. You can use the hard memory controllers for LPDDR2, DDR2, and DDR3 SDRAM interfaces. Compared to the memory controllers implemented using core logic, the hard memory controllers allow support for higher memory interface frequencies with shorter latency cycles.

The hard memory controllers use dedicated I/O pins as data, address, command, control, clock, and ground pins for the SDRAM interface.

On the page 36 "Hard Memory Controller Width for Cyclone V E" there is the text "Table 6-16: Hard Memory Controller Width Per Side in Cyclone V E Devices" which says that in the selected 484 version of Cyclone V E there are 24 pins (top) and 24 pins (bottom) for memory data (DQ) with hardware memory controller.

So, I have two hardware memory controllers with 24 bit width each.

Can I use them to use the full-size DDR2 or DDR3 memory module (like modules used in my PC or in my notebook). According to several pdfs, the 240-pin PC modules (and 204 pin notebook modules) are usually configured as 512Mx72 or 512Mx64. I read this Module configuration as memory with 72 (ECC) or 64 (non-ECC) data pins.

I think, that count of hardware pins in my FPGA is less then data width.

Can I merge two hardware controllers of 24 pin into single 48 bit controller and use the module?

Can I use module, if I don't drive part of pins?

Can I split module into two parts, using left part independently of right part, each part with own addresses?

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No, you can't.

You are only taking into account the data pins, but a DDR has other pins, address and control. Each one of the two banks has its own address and control pins. You cannot merge them together.

You are limited to a maximum data width of 24 bits. And even if you decided to limit yourself to 24 bits, there are other considerations on how you can connect a DDR interface to a device, as opposed to a DIMM. You have to check other pins compatibility, timing, clock, etc.

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