# PMOS Turn-On due to gate capacitance?

I just stumbled over a quirk in my simulation. I have a fairly standard PMOS gate drive with a capacitor C1 for controlling inrush current during turn-on.

EN input is normally high and pulled low when fault is detected. Since the fault detection logic is only active after VDD provided by a Zener has stabilized Q1 should be open, but the gate is pulled up by R2. Furthermore, Q2 is controlled by voltage detector that pulls to VDD once the detection circuitry is online, thus Q2 also blocks.

What I don't understand is, how M1 can turn-on by a step on Vin when it's gate is pulled to Vin by R2 and the connection to ground is blocked by Q3.

Also, what can I do against this behaviour? Or is this a non-issue and only present in simulation?

I checked also with rise time up to 10ms but the effect is still there. simulate this circuit – Schematic created using CircuitLab

• Look at the collector current of Q2 in your simulation. I suspect it is something not shown on your schematic here. I presume there's a resistor in series with EN.. Apr 11, 2014 at 8:53
• The collector current of Q2 is in the range of nA. EN of Q3 is tied to VDD which is slowly rising towards 2.5V.
– Arne
Apr 11, 2014 at 9:02
• If you graph the collector current of Q2 vs. time it never rises above some nA? Apr 11, 2014 at 9:20
• @SpehroPefhany Correct. Even when I leave R3 open the effect persists.
– Arne
Apr 11, 2014 at 9:25

That's no quirk, it's exactly what would be expected. M1 is turning on when Vin is applied. Any FET can be forced to turn on when a sufficiently high dV/dt is applied from drain to source. Charge is injected into the gate through $C_{\text{dg}}$ (the Miller capacitance) as $V_{\text{ds}}$ changes. Gate voltage then exceeds $V_{\text{th}}$ and the part conducts as long as dV/dT continues.

If the goal is to slow the rising edge (turn on) of the drain, using and increasing $C_{\text{dg}}$ is a good way to do it. It must be realized that sensitivity to dV/dt will be increased, however. Increasing $C_{\text{dg}}$ is especially effective since it is multiplied by FET $g_{\text{fs}}$, so less capacitance will be required for a given rise time (compared for example to increasing $C_{\text{gs}}$). The problem here is that C1 and R2 are so huge that the circuit will be extremely sensitive to dV/dt.

Older technology FETs have maximum dV/dt ratings specified, usually ~5V/nSec (from the IRFZ44 datasheet for example). Parts could be made to conduct, even with the gate shorted to ground, by applying that type of voltage change across the drain to source. It's possible to use the specified dV/dt and $C_{\text{dg}}$ to calculate what the internal $R_g$ of those FETs is ... it usually works out to be ~10 Ohms. Who cares about old technology FETs? In this case, the numbers involved will make a nice tool for cocktail napkin analysis.

So, dV/dt = 5V/nSec, $R_g$ = 10 Ohms, and $C_{\text{dg}}$ = ~100pF. C1 in your circuit augments $C_{\text{dg}}$, in effect becomes $C_{\text{dg}}$. Since C1 is about 1000 times more than the $C_{\text{dg}}$ in the FET, the circuit will be about 1000 times as sensitive to dV/dt as without C1. Or, would turn on with dV/dt of ~50V/uSec, and that's with $R_g$ of 10 Ohms. But, $R_g$ isn't 10 Ohms in your circuit, instead it's 220 kOhms (R2), which makes the circuit an additional 22,000 times as sensitive to dV/dt. Oh, and must not forget that those were high threshold FETs, so a new lower threshold FET would increase the sensitivity by about a factor of 4. Combined the limit for dV/dt that would be reasonable from a cocktail napkin scribble would be (5V/nSec)/((1,000)(22,000)(4)) or about 57V/Sec.

How slow does the drain rise time need to be? Even C1 of 1000pF would slow the turn on significantly.

For this circuit to be useful though will require Q1 be on while Vin is applied to keep gate impedance and dV/dt sensitivity low.

You're just measuring the ~340pF Drain-Source capacitance of M1 to your output load.

It's not really turning on.

If you put a realistically large capacitor on the output (eg. uF) and slow the input rise time to something sensible it should pretty much go away.

• I'm not sure whether I understand you correctly. It seems that the effect diminishes when I remove C1.
– Arne
Apr 11, 2014 at 12:39
• Did you try what I suggested (simulate with a 10uF load capacitance and power rise time of, say, 100usec)? Apr 11, 2014 at 12:43
• I did. I then have a 3.6A peak current charging the load capacitor and the voltage at the drain then steady at the Vin level due to lack of a discharge path. When I add a load resistance the drain voltage then decays slowly towards zero.
– Arne
Apr 11, 2014 at 12:46
• I added some parasitics to the cap and the problem persists. I also tried with some serial resistance in the until-then ideal voltage source but to no avail.
– Arne
Apr 11, 2014 at 12:55
• If M1 is removed, the problem goes away? D1 also has some capacitance, but it's shunting the gate. Apr 11, 2014 at 13:05