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I'm new to verilog and HDL, so please be patient with me.

In a code, I have an input variable clk, two input 16 bit samples, that are stored into [31:16] ddc_out_sample and [15:0] ddc_out_sample and an input strobe called ddc_out_strobe.

What I want to do is take the 8 MSB bit of [31:16] ddc_out_sample and [15:0] ddc_out_sample, having a 16 bit sample instead of a 32 one. Then combine 4 of those samples to feed them directly to the output [31:0] bb_sample. The output strobe is bb_strobe.

I had thought of the following implementation to achieve this:

reg count = 0;

always @(posedge clk)
     i_msb <= ddc_chain_out[31:24]
     q_msb <= ddc_chain_out[15:8]
     assign bb_strobe = 1'b0;
     if(count % 4 == 3) 
        assign bb_strobe = ddc_out_strobe;
     end
     count = count + 1;
end

I know that asynchronous conditions should be avoided, but I don't see how to implement this otherwise.

Any comments and thoughts will be appreciated.

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1) Don't mix = and <=, they have different meanings and some tools will object.

2) "assign" is basically wiring one thing to another, it should not be used in "always" blocks.

3) You've not assigned bb_sample.

My version:

// 'reg' by itself is a single bit, need two bits for 0-3
reg [1:0] count = 0;

always @(posedge clk)
   if (ddc_out_strobe) begin
     i_msb <= ddc_chain_out[31:24];
     q_msb <= ddc_chain_out[15:8];
     if(count == 2'd3) 
         bb_strobe <= 1'b1;
         count <= 2'b0;
     end
     else begin
         count <= count + 1;
         bb_strobe <= 1'b0;
     end
   end
   else begin
      bb_strobe <= 1'b0;
   end
end
| improve this answer | |
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  • \$\begingroup\$ Thanks! Assigning bb_sample could be done by something like bb_sample <= [31:0]{i_msb,q_msb,bb_sample}? What I am aiming for there, is to store the newest samples there, disregarding the parts of bb_sample that I no longer need (not sure if that syntax is allowed though...) \$\endgroup\$ – titus.andronicus Apr 11 '14 at 10:08
  • \$\begingroup\$ bb_sample <= {i_msb,q_msb,bb_sample[31:16]} would be valid; tragically you can't do subselects off anything that isn't a reg or wire. \$\endgroup\$ – pjc50 Apr 11 '14 at 16:38
  • \$\begingroup\$ And how about when ddc_out_strobe, bb_sample, ddc_chain_out and bb_strobe are wires? I know that wire elements cannot be used as the left-hand side of an = or <= sign in an always@ block. But how to assign them if that is now allowed? \$\endgroup\$ – titus.andronicus Apr 16 '14 at 7:39

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