# PMOS Inrush Current Limit - Where to place Capacitor

In order to reduce back-EMI of a Buck converter a LC input filter is to placed in front of the converter. To limit the inrush current when those caps are charged I consider to use a PMOS with a RC filter at its gate.

The following schematic shows the whole input stage including inrush current limiter (M1), reverse voltage protection (M2) and fuse.

During simulation I noticed that placing a capacitor from gate to source (C5) is much more effective in limiting inrush current than placing it from gate to drain (C4). This contradicts sources on the net like here that show the capacitor from gate to drain. Is the effect I see only in my simulation or is this due to the fact that I don't actively drive my PMOS but effectively tie it's gate to ground?

simulate this circuit – Schematic created using CircuitLab

It is usually beneficial to use feedback around an active device, like C4 would provide to M1, when you can. That lets the gain of the amplifier work for you. Let's see how it works out by comparing the two situations separately.

As a thought experiment about the effectiveness of C4 and C5 for inrush current limit, consider the two plots (generated using a 1st order model of the FETs). Vin is set as 25V. Load capacitance is 31uF. FET modeled was SiA441. Gate resistance (R2) was 30 kOhm, and gate voltage for turn on was set to get about 100uA of gate charging current in the Miller switching scenario. The same gate drive setup was kept for the passive RC case. In each case time required for the gate to rise to $V_{\text{th}}$ were removed to get rid of switching delay.

The first plot shows C5 of 68nF without C4, so just a passive RC on the gate to slow down turn on. Peak rate of rise of drain voltage is about 5V/35uSec, for a peak charging current into 31uF of 4.5A. Most of the charging takes place in about 200uSec.

Second plot shows C4 of 1500pF without C5, using the Miller effect to slow down turn on. Value of C4 was reduced from 68nF to 1500pF to have turn on be between 400 and 500 uSec. Rate of rise of drain voltage is about 5V/100uSec, or about 1.6A charging current into 31uF.

If the only concern were turn on time and inrush current, the configuration using C4 and the Miller effect would be the way to go. But, there are other things going on, so let's look at those.

dV/dt

The circuit as drawn would have dV/dt turn on for Vin rise rates faster than 23V/Sec. Here are dV/dt limits of 4 configurations for C4 and C5.

$\begin {array} {ccccc} \text {Case} &\text {C4} &\text {C5} &\text {R1} &\text {dV/dt} \\ 1 &\text {68 nF} &\text {68 nF} &\text {330 kOhm} &\text {23 V/Sec} \\ 2 &\text {100 pF} &\text {68 nF} &\text {330 kOhm} &\text {--} \\ 3 &\text {1500 pF} &\text {800 pF} &\text {330 kOhm} &\text {1000 V/Sec} \\ 4 &\text {1500 pF} &\text {68 nF} &\text {330 kOhm} &\text {25 kV/Sec} \end {array}$

dV/dt was calculated using the equation in section 2 of "Calculating the pulldown resistance for a given MOSFET's gate"

$V_{\text{th}}$ of 0.5V was used since that matches the Si2367. Lower $V_{\text{th}}$ is not always best. If a FET with a $V_{\text{th}}$ of 2.5V were used, dV/dt would be 5 times as high. Case 2 is the only case that doesn't show a dV/dt limit. Case 3 and 4 could have dV/dt improved by using a higher $V_{\text{th}}$ FET and reducing R1 and/or using an under voltage shutdown.

Gate Control

Higher charging current into the gate will make either configuration switch faster with higher inrush current. Gate drive is completely dependent on Vin level and rate of rise. Neither configuration will function well without a more controlled gate.

A current source in place of R2 could help a lot. Current regulator diodes (like S-101T), are simple to use. As you point out, a depletion mode JFET (like the MMBf4416a) with a trim resistor could be used too, although you might have do some part selection. Also, could consider the LM611 (see figure 61 for use as a current source). You might think this is insanely expensive too, but you get a reference and an amplifier that work from 4V to 36V. Maybe use the OpAmp as part of UV shutdown. Finally, maybe the LM334 as current source. It's not fast (may take 50 or 100uSec to settle) but is cheap and works from ~1V to over 30V.

• These current limiting diodes seem insanely costly. However, since they seem to be nothing more than an N-Ch. JFETs plus resistor, is it feasible to build one's own? For example using a MMBF4416A? – Arne Apr 22 '14 at 17:30
• Current regulator diodes are just depletion JFETs, but are trimmed, so they are simple and accurate. Could use something like a MMBF4416 for prototype quantity if you don't mind trimming. Wasn't trying to steer to a specific part, just wanted to give a tangible idea. – gsills Apr 23 '14 at 3:11
• So the benefit of C4 is that the capacitor can be smaller for the same time delay? And why does the plot says "Vds"? Wouldn't that drop to zero as the FET turns on? – endolith Aug 29 '16 at 18:22

I assume you mean "C5" as the gate-to-drain capacitor, not "C6".

I'm not sure what you mean by "more effective". Yes, it takes a lot longer to charge C4 than it does to charge C5, because you're depending initially on the leakage current through M1 to get things started. But this current will vary a lot from part to part (and with temperature), so you can't really depend on it being any particular value.

It would be better to use C5 and set the R-C time constant to what you need. This will be a lot more repeatable.

• That makes a lot of sense. However, why is the opposite setup (gate to drain) mentioned so often? – Arne Apr 16 '14 at 15:08
• @Arne It's not always: Figure 1 shows the cap before the FET. – endolith Aug 29 '16 at 21:23