In Pong Chu's "FPGA Prototyping by Verilog Examples" he recommends using a periodic enable "tick" to divide the clock while maintaining a synchronous system (to avoid putting the system clock through combinational logic).
The example for a counter (r_reg) generating a "tick" uses a mux and comparator:
assign max_tick = (r_reg == TICK_VALUE) ? 1'b1 : 1'b0;
Example of generating the tick (simulated):
Things seem to simulate fine using this description; But, is there any reason to be worried about violating hold time for the next element in series when using the output tick generated in this manner as an enable signal? If not why not?
To clarify, my understanding is that the enabled device would see the tick in the above example at the out=0000 rising clock edge, but the tick is already being driven low again by that clock edge - would there be a concern over violating the hold time?