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I used LPM_RAM to store data and made read and write operations. But it seems like placing the data to wrong addresses. Here is screenshots;

Wave Result;

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Memory Block;

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  • \$\begingroup\$ Some of the signals in the "scope" plot I am not seeing in the schematic -- M_ADDR, M_INP and M_OUT. \$\endgroup\$ – gwideman Apr 18 '14 at 14:19
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Well, it's pretty hard to read the diagrams, I can't see the crucial M_ADDR, M_INP and M_OUT on the diagram as I said in the comments, and I know nothing about Quartus II, so I feel ideally qualified to comment...

Looks to me like you have either a stage of latches either in the address path or in the data out path which is causing the displayed output data to be one clock cycle delayed relative to the displayed address.

enter image description here

So it's not reading data from the wrong address, it's just delayed.

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  • \$\begingroup\$ M_ADDR is ADDR, M_INP is Input and M_OUT is Output. So, can we say that, writing operation takes 1 cycle and reading operation takes 2 cycle? \$\endgroup\$ – Cem Apr 18 '14 at 14:32
  • \$\begingroup\$ You tell me -- I can't really read the diagram. How many latch stages are there in each path between address and the destination of the data? \$\endgroup\$ – gwideman Apr 18 '14 at 14:35
  • \$\begingroup\$ Also, there's a distinction to be made between clock cycles per read, versus read latency. \$\endgroup\$ – gwideman Apr 18 '14 at 14:38
  • \$\begingroup\$ I don't know how to look inside RAM. Maybe I should read its documentation. What's its relation with latches? \$\endgroup\$ – Cem Apr 18 '14 at 14:40
  • \$\begingroup\$ So, all my operations that needs memory read cannot be done in one clock pulse. Is it true? \$\endgroup\$ – Cem Apr 18 '14 at 14:42

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