I have SN74HC4040 12 bit counter, however, I need only 10 bits and then reset it back to 0. Would it be reliable to use 11th bit as an input to the CLR (reset pin)? Basically, when the counter transitions from 1023 to 1024, the 11th bit becomes high, which, in turn, sets CLR to high and resets the counter. It seems to work, but I do not know how to check the counter's state during the reset period.

  • \$\begingroup\$ I wonder if you may miss the 0 count since it async clears when clk is high and increments on a high to low transition of clk. \$\endgroup\$ – HL-SDK Apr 18 '14 at 15:56

You don't need to do any of that. Simply ignore the upper 2 bits. Now you have a 10 bit counter that automatically wraps around from 1023 to 0.

  • \$\begingroup\$ That's easy! But in general, would it work to reset itself? \$\endgroup\$ – Nazar Apr 18 '14 at 16:16
  • \$\begingroup\$ @Naz: It's hard to say because it could create a race condition. You have to look carefully at the timing contraints of the specific counter you plan to use. It might also add one more count to the sequence, like 0-1024 instead of 0-1023. It can be tricky, and you have to read the counter datasheet very carefully. \$\endgroup\$ – Olin Lathrop Apr 18 '14 at 16:23
  • \$\begingroup\$ well, I will just forget about it. \$\endgroup\$ – Nazar Apr 18 '14 at 17:01
  • \$\begingroup\$ Naz - No, with a little extra it will work fine. The problem is that you can have the reset function act on the bit 11 flip-flop before some of the others have completely finished. In this sense, want you want to do is extremely unreliable, and may vary with temperature and power supply voltage. All you need to do is put a couple of gates between the bit and the clear input. A couple of 74HC04s will do the job just fine. This will delay the end of the reset pulse long enough for reliable operation. \$\endgroup\$ – WhatRoughBeast Apr 18 '14 at 17:53

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