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I am working on a project which requires communication of data between Xilinx Spartan 6 FPGA (XC6SLX45T-2FGG484) and OMAP 3530, I have a ULK dev board on which

  1. The 32Kx8 (256Kbits) serial electrically erasable PROM (24AA256-I/SM) from Microchip is used to interface with OMAP processor through I2C interface.

  2. The same 32Kx8 (256Kbits) serial EEPROM (24AA256-I/SM) from Microchip is used to interface with FPGA through I2C interface. The I2C is common to both processor and FPGA.

  3. The GPMC bus of the OMAP3530 processor is used to communicate with Spartan-6 FPGA for register read/write and for programming the FPGA. here GPMC controller signals of OMAP3530 Processor will be Configuring in address/data non-multiplexed mode. As well as Chip select signals (CS0-4), SPI3, I2C3 and GPIO signals will be connected to FPGA for misc communication. To generate interrupt from FPGA Processor two dedicated GPIO signals are used.

Now I am not sure where to start,

  1. what is the choice

a. can I use the EEPROM as like shared memory into which processor and fpga perform r/w operations. what would be the feasibility and speed implications of such an implementation.

b. can I Use GPMC misc communication part..? how shall I go about it?

which of the two would be more appropriate? and how shall I move ahead, kindly forgive my ignorance,if I made some mistakes or interpreted data wrongly.

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  • \$\begingroup\$ Just a simple question, do you have a multi-master I2C IP for the FPGA? \$\endgroup\$ – FarhadA Apr 19 '14 at 9:31
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The GPMC should be the way to go. Basically, what you need to do is write an FPGA configuration that implements a port that acts like a GPMC compatible SRAM. However, instead of accessing an SRAM bank, the port can access various registers and memories inside the FPGA. If you use the correct pins for the data side of the port on the FPGA, then you can use the SelectMAP configuration method and you can write the configuration data to the FPGA in parallel very efficiently. When writing the configuration data, no address pins are used, so you can use whatever pins are convenient. You may need to have a little fun with the control signals and CCLK as many of these pins are not accesible from the FPGA design - as in, you may need to connect the CCLK pin and another IO pin to the CPMC clock pin. It's possible that you will need some discrete logic as well to make everything work.

I would not recomend using the EEPROM unless you need nonvolatile storage. The number of write cycles is limited, so it could get worn out quickly.

If communication is needed from the FPGA back to the OMAP, I would recommend adding and interrupt line from the FPGA and then reading the necessary data over the GPMC interface in an ISR.

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