I was wondering if anyone knows an efficient way to program the FPGA(PL) for a Xilinx Zynq-7 series or related devices,from a host C program (not on the SoC, but from the host PC). Is there an Xilinx API I can use/include in my program. As the only way I can think of doing it at the moment is invoking command line programming via Impact (which is not very elegant).

Basically I want to put the SDK "Program FPGA" functionality in my host C program where the user selects a prebuilt .bit file (and .elf file if possible) to program the FPGA/(SoC). This is just for a test of concept, later I would like to put this dynamic configuration onto one of the ARM CPU's.

Many Thanks Sam


2 Answers 2


Depends on how you're connecting the FPGA to the host. If you're using the Xilinx JTAG cable, you're pretty much stuck with Impact. However, if you have a different interaface to the host, then it would not be too difficult to, say, write a loader interface that can accept a bit file and overwrite the configuration flash. Then all you need to do is reboot the board, and you're good to go. I would suggest loking at the Xilinx configuration guide for the part you're using; it will have more specific information about the various configuration interfaces.

Edit: Interesting; there isn't a separate config guide for the Zynq parts. Take a look at chapter 6 of the technical reference manual, Xilinx ug585. Loks like the procedure is to boot one core from flash, then have the core load the FPGA config. If you can load a new config into RAM over any arbitrary interface, then as long as resetting the programmable logic portion does not stop the core from accessing the image in RAM, you can reset the FPGA and load the new configuration from RAM. Looks like you need to use AXI-PCAP. I would imagine that you can also update the ARM core software, but I am not sure what the proper prcedure would be. Do you have any external program memory, or are you only utilizing on-chip memory? If you can use external memory, then maybe you can 'stage' a new image in external memory, then copy it back into internal memory before starting it. Bascally, you just need a way to squirrel away a little bit of code that can reload the FPGA configuration and then reload and/or start the ARM core software.


Xilinx has a very good applications note with supported C code you can use as base for your code.

For your controller to work you must have 4 free GPIOs and connect them to the FPGA (and the other JTAG devices in the chain) as shown in this image:

JTAG chain

You might have to change it a bit to adapt it to your own environment but basically you need to go trough the steps described in the app-note, previously I used the XSVF format to program the FPGA using a Cortex M3 controller, for that I followed these steps:

How to create XSVC file for Xilinx

You can search Xilinx for XAPP058 : "Xilinx In-System Programming Using an Embedded Microcontroller" on their web site, it is a bit old, but you might be able to find the latest one that works with the new devices as well.

  • \$\begingroup\$ is this using a custom board? As at the moment I am just using the Zedboard so that could be where my problem is! \$\endgroup\$
    – Sam Palmer
    Apr 21, 2014 at 8:55
  • \$\begingroup\$ After reading a lot of docs and forums I think i must conclude that using the ARM cores is probably the only way (using PCAP) unless I want to use command line Impact. This does pose the problem though that I can't configure the ARM cores using the .elf files corresponding to the software which drive the PL. \$\endgroup\$
    – Sam Palmer
    Apr 21, 2014 at 10:46
  • \$\begingroup\$ Looks like configuration for the Zynq devices is very different from other FPGAs. The boot sequence listed in the manual indicates that the ARM core boots up first, and then the user code can load the FPGA image. I suppose it is possible to do this again after bootup, presuming that stopping the FPGA does not prevent the operation from completing. Is this for a dynamic reconfiguration setup, or just for a rare firmware update? Maybe the best solution is to rewrite the configuration memory and reboot. \$\endgroup\$ Apr 22, 2014 at 2:22
  • 1
    \$\begingroup\$ Well, Xilinx has a detailed description and a reference design for the Zynq FPGAs using the XPS. This was something new for me, I have not tested it myself, but it looks pretty straight forward to do so: wiki.xilinx.com/… \$\endgroup\$
    – FarhadA
    Apr 22, 2014 at 8:44

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