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Can anyone tell me as to how I should write behavioral description for a latch in VHDL? Since it's level-sensitive, will the below line of code represent a latch?

if clk='1' then Q<=D;
end if;
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The code you show is a snippet of sequential code, and it may model a latch if the rest of the process is correct.

How about writing it in concurrent code?

Q <= D when clk = '1';

Or, if you want to be extra terse and VHDL-2008 is an option:

Q <= D when clk;
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