2
\$\begingroup\$

my configuration:
H-bridge with 4 n-ch mosfets (IRF1405) with a gate capacitance of 5480pF and turn on delay time 13nS. I am using a hip4081 as my driver which has a peak current of 3.8A! This is how I am calculating the max pwm frequency my circuit can handle:

V=IR---(1)
t=RC---(2)

from (1) R=V/I plug in (2) => t=(V/I) * C where
V=Gate Voltage (10V)
I=Max gate current (3.8A)
C=Input gate capacitance (5480pF)

plugging these values I get t = 14.4 nS. now this is the time it will take to charge the gate capacitance and so my pwm frequency should be < 1/t?

does this sound right? Please add your insights.

EDIT
Load is a wheelchair motor
Power = 150 - 450 W Voltage = 24VDC I = P/v = 7A - 19A

\$\endgroup\$
  • \$\begingroup\$ I think you may have to add informations about load. Resistive load may allow high frequencies, but adding some capacitance or inductance may change everything. \$\endgroup\$ – Kamil Apr 22 '14 at 23:04
  • \$\begingroup\$ Please read the data sheet for the hip4081. "The HIP4081A can switch at frequencies up to 1MHz". Your calculation give an approximate turn-on time for the FETs. You want the actual conduction time to be a good deal longer than this if you want decent efficiency. \$\endgroup\$ – WhatRoughBeast Apr 23 '14 at 0:59
  • \$\begingroup\$ Is it a brushed DC or PM? Usually for motors, PWM frequency doesn't need to be too high ... 20 or 30kHz. \$\endgroup\$ – gsills Apr 23 '14 at 3:37
  • \$\begingroup\$ it is a DC motor. \$\endgroup\$ – rashid Apr 23 '14 at 13:13
3
\$\begingroup\$

The gate charge time isn't really that simple. There's the Miller effect as the FET transitions through the linear region and has negative voltage gain. This causes the gate to drain capacitance effectively to be many times larger than the actual value. The driver doesn't necessarily put out the peak current throughout the whole voltage range either. The total gate charge curve on the datasheet can help get a better estimate for gate rise time.

Having said that, 14ns sounds pretty close to what the real gate rise time will likely be. The question of what the maximum switching frequency can be leads to the question: What's your target efficiency? How much power are you willing to lose to switching losses? If your switching frequency is on the order of your risetime your switching losses will be extremely high. If you want a rough guideline switching an H bridge at 1MHz and above can be done, but starts to get tricky and lossy. 100-300kHz is a good range. Note that this is many times the risetime, but will allow reasonable efficiency.

My rule is switch at the lowest frequency possible while still meeting size and system constraints (out of audio band, etc.). This maximizes efficiency and minimizes EMI.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.