# Required output impedance for ADC input?

On the Atmel ATmega328P on the Arduino Uno, the ADC RAIN value is 100 MΩ - which I assume is the ADC input impedance. However, in the datasheet it says "The ADC is optimized for analog signals with an output impedance of approximately 10 kΩ or less."

How do you figure out the ideal output impedance to work with the ADC? I'm trying to figure out how this applies to other discrete ADCs which have an input impedance that varies with sampling frequency. For example, on one part the input impedance varies from 125 kΩ to 65 MΩ. How would I figure out what the max allowable input impedance should be?

Also - am I even asking the right questions here or am I missing something huge?

• How do you figure out the ideal output impedance to work with the ADC? The output impedance should be as lower as possible, ideally being zero.. Apr 24, 2014 at 9:02
• To solve that problem you have there with large impedance, just use a buffer (op-amp buffer will do). Apr 24, 2014 at 17:01

In case you are left wondering how the input resistance is spec'd as 100 MΩ, yet the impedance recommended driving for driving the input is 10 kΩ: The following diagram illustrates the input to the ATmega328P A/D: As KyranF described, the task of your external circuitry is to ensure that the sampling capacitor CS/H gets charged to a voltage that's within some percentage of the input voltage, within the sampling time. The charging process is slowed by the resistance of your voltage source, and by the resistance of the circuitry between the ADCn pin and the sampling capacitor, here shown as "1..100 kΩ".

(That "1..100 kΩ" is a vast range, and I would be interested what the range actually is in practice.)

Not shown in the diagram are additional small capacitances associated with the multiplexer. And RAIN is also omitted, as it's insignificant compared to IIH and IIL (max 1μA).

The recommendation that your voltage source be less than 10 kΩ is essentially saying that we don't want the source resistance to slow the charging of CSH (and any other capacitances) significantly compared to the already present resistance, and relative to the sampling time. (However, the "1..100 kΩ" doesn't back that up very rigorously.)

Looking at this from another point of view, the supposed "100 MΩ" input resistance of ADCn pins is not the whole story. RAIN is parallel with IIH and IIL , which, when selected is also parallel with the "1..100 kΩ in series with 14 pF" load.

In the sense that the 100 MΩ || IIH || IIL represent the entirety of the DC characteristics, it is legitimate, but it's not the relevant part of the load for our design purposes. We need to design to drive the "1..100 kΩ in series with 14 pF" AC part of the load, which Atmel tells us is best done with a 10 kΩ source resistance.

(Note that in discussions the term "impedance" may or may not imply that non-resistive AC characteristics are expected, and is sometimes used where what is really meant is "resistance".)

[Edit -- cuz this turns out to be quite interesting...]

Adding some ballpark sample and hold settling times:

With R = 100 kΩ and C = 14 pF, the RC time constant (TC) is 1.4 μsec.

For ATMega, the S/H time is 1.5 cycles of the ADC clock. For a midrange ADC rate of 100 kHz, that puts the S/H time at 15 μsec. So that's a bit over 10 TC.

The voltage on a capacitor settles to within 37% of its final value in one time constant, 5% in 3 TC, 1% in 5 TC and 0.1% in 7 TC (corresponding to +/- 1 bit of 10-bits resolution).

You can see that doubling the input R to 200 kΩ, or doubling the A/D clock rate, will chew into the resolution. But a change of input R from 10 kΩ down to 1 kΩ doesn't do us much good... though it could be beneficial for external reasons, like lower sensitivity to neighboring noisy signals.

Hope that helps.

• indeed! good expansion on my ramblings haha Apr 24, 2014 at 0:31
• If you are not sampling too frequently, you can add a capacitor - say 10nF, with a 14pF input capacitance, you are down to about 0.14% error, even if your sampling time is tiny. If you check your number of time constants between samples given the external cap and the resistance, this is often plenty good enough. Jan 15, 2021 at 23:32

How do you figure out the ideal output impedance to work with the ADC?

By reading the datasheet. You even quoted the section that tells you this answer on a silver platter: The ADC is optimized for analog signals with an output impedance of approximately 10 kohm or less.

So the answer is feed it a signal that has 10 kΩ or less impedance.

The internal sampling capacitor of an ADC peripheral in your Arduino Uno's ATmega328P needs to charge, so you can sample it right? Well, in this case the internal resistor (input impedance) has been given as 100 MΩ. The capacitor needs to be charged by the analog source with <= 10 kΩ, so that it will be charged enough ready for sampling. If you charge the capacitor too slow, you will have scale error/false readings.

It's possible that if you have a terribly slow/weak analog input you should put a voltage buffer op-amp in unity gain - and find one with extremely low offset voltage/bias current, and high enough bandwidth/slew rate (so it doesn't affect your signal as good as possible), with a output resistor of 5-10 kΩ to drive your ADC inputs fast enough.

Every microcontroller that has an internal ADC peripheral, and the many dedicated ADC ICs, are different and they will all need special attention to things like this, so it's good that you read about it and have asked questions about it.

• Regarding this: "with a output resistor of 5-10K Ohm to drive your ADC inputs fast enough." Is it necessary to place a resistor there? Another person mentioned that 0 output impedance is ideal. Is it a bad practice to drive the ADC input straight from the op amp?
– Pugz
Apr 24, 2014 at 13:44
• Well if you wanted ultra fast sampling then as low impedance as possible is best, so no resistor. The opamp itself has inherent output impedance, but it is very low. I think the resistor is good for slowing down current spikes into the sampling capacitor. Slowing things down a bit is a safe assumption! If you can spare the PCB space and component count, I would advise you to do it. Apr 25, 2014 at 0:38

The ADC inputs are capacitive. As you know, a capacitor is basically open circuit, so the input resistance is the resistance across (among other things) the insulator of the capacitor. It should be high, as expected :)

And that's why DC resistance is of no big use, because the input's behavior varies with time: the capacitor gets disconnected from the input, and then connected again, and the input must provide enough current to charge the capacitor in the time window provided in the datasheet.

So, in the discrete ADC datasheet you'd look for the equivalent input circuit to determine the sampling capacitance, and the ADC timing specification to determine the duration of the sampling phase. The output impedance of your circuit should drive that capacitor to a sufficiently accurate voltage within the sampling phase when the capacitor is connected to your output. The number of RC time constants, where R is your output resistance and C is the sampling capacitance, that should fit within the sampling phase linearly depends on the sought accuracy expressed in a log scale (e.g. number of bits of accuracy).

If Iih and Iil are max'd at 1uA, then 10K source can cause a 10mV error, under such worst case. If using the internal Varef, then this is about 10 lsb's worth, which is a lot. You can add a shunt capacitor, say 0.1uF to ground, if your signal bandwidth is very small, e.g. measuring dc levels, but if your source resistance if high, you will need a buffer to provide a lower source resistance.

• The problem is not due to leakage current. The other answers already explain why impedance lower than 10k is necessary. And a buffer is not necessarily needed if source impedance is high, the 100nF capacitor you proposed will bring down the impedance to low enough level - but sampling rate needs to be limited so it has a chance to charge up between conversions. Jun 30, 2021 at 20:11