# CPLD: my first project

First, I posted similar question on CPLD/FPGA users forum, however, they do not seem to be as active as StackExchange. So, I hope it will help me to get going with CPLDs and also will be useful information for other starters.

After little research I was convinced to focus on Xilinx CPLDs because, in opinion of some people, it seems to be more student friendly and the vendor provides free software. I do not have a development board or the chip - just trying to simulate first before buying. So, after downloading ISE WebPack software, I begun my first tutorial. I got stuck on the "Implementing a New Top-level Design" step 5. It fails to 'fit' the design:

The log gives me the answer to my error, but I truly do not know what to do next. Although I followed all the steps from the tutorial, there is probably something I am missing? I tried to Floor Plan IO and assign IO pins, but it did not help. Any ideas? Any other good tutorials for absolute starters?

Here's the script:

• The first warnings appeared during synthesis and I suspect that they hold the key. – Joe Hass Apr 25 '14 at 14:35
• You could post the code for more details advice, but the error message tells you a lot - you don't seem to have any output ports, so there's ultimately no design for the fitter to place. – fru1tbat Apr 25 '14 at 14:36
• @fru1tbat What should I do to make a design? The tutorial does not foresee that. – Nazar Apr 25 '14 at 14:45

There is nothing in the architecture of your design, so it synthesizes to no gates. With no gates there is nothing to connect to the output signals, so the output signals are deleted. Likewise, the input signals are deleted because they connect to nothing. Therefore, there were no pins and no gates to fit into the design. I'm pretty sure the warnings from the synthesis step would have told you this.

• Yes, you are right. But what do I have to do to create architecture? Do you know a good tutorial on CPLDs that will guide me through all the necessary steps beginning with creating a project and finishing with simulation? I just can not understand which step is skipped in the tutorial that I referenced in my question. Apparently this step does not let me to move forward. – Nazar Apr 25 '14 at 14:58
• You need to write the VHDL code that describes the behavior you want from the hardware. If you don't know how to do that then you should step back from the design tools for a bit and learn about VHDL. – Joe Hass Apr 25 '14 at 15:21
• Shouldn't pins remain whether or not they connect to any logic, since the configured options on a pin may affect its electrical behavior [e.g. if there are bus-keepers, etc.]? While most configuration options affect electrical behavior, I wouldn't expect synthesis logic to distinguish those that do from those that don't. – supercat Apr 28 '14 at 16:18
• The synthesis tools try to optimize your design unless you explicitly prevent them from doing that. Optimization includes removing any logic or pins that have no effect on the function of the design. If there is no signal going to an output pin then the synthesizer has no idea what to do with that signal. What difference does electrical behavior make if the logic value is undefined? – Joe Hass Apr 28 '14 at 17:53
• Yep, reading this book from the page first to the page last helped to solve the problem. – Nazar Apr 28 '14 at 19:21

The Example project should contain the correct code.

This page indicates to open the jc2_abl project. This is found either by navigating to your ISEExamples directory in your ISE install (what they suggest you do, found in <Install Dir>/14.5/ISE_DS/ISE/ISEexamples), or by File -> Open Example.

My particular install of ISE didn't have jc2_abl as an example, but did have jc2_vhd, which contains the vhd code for the example, copied here:

library IEEE;
use IEEE.std_logic_1164.all;            -- defines std_logic types

entity jc2_top is
port (
left  : in  std_logic;                     -- Active-low switch #3 (left)
right : in  std_logic;                     -- Active-low switch #0 (right)
STOP  : in  std_logic;                     -- Active-low switch #2
CLK   : in  std_logic;
Q     : out std_logic_vector (3 downto 0)  -- Active-low LEDs
);
--To pass pin location constraints from this HDL source file rather than
--through a User Constraints Format (UCF) file, uncomment the six attribute
--declarations below and remove jc2_top.ucf from the project.
--    attribute pin_assign : string;
--    attribute pin_assign of clk : signal is "A7";
--    attribute pin_assign of left : signal is "G7";
--    attribute pin_assign of right : signal is "B2";
--    attribute pin_assign of stop : signal is "F2";
--    attribute pin_assign of q : signal is "G5 F6 C6 B4";
end jc2_top;

architecture jc2_top_arch of jc2_top is
signal DIR   : std_logic                     := '0';     -- Left=1, Right=0
signal RUN   : std_logic                     := '0';
signal Q_int : std_logic_vector (3 downto 0) := "0000";  -- Internal signal driving Q output; Active-low LEDs
begin

process (CLK, right, left, STOP, RUN, DIR, Q_int)
begin
if (CLK'event and CLK = '1') then   -- CLK rising edge
-- DIR register:
if (right = '0') then
DIR <= '0';
elsif (left = '0') then
DIR <= '1';
end if;

-- RUN register:
if (STOP = '0') then
RUN <= '0';
elsif (left = '0' or right = '0') then
RUN <= '1';
end if;

-- Counter section:
if (RUN = '1') then
if (DIR = '1') then
Q_int(3 downto 1) <= Q_int(2 downto 0);  -- Shift lower bits (Left Shift)
Q_int(0)          <= not Q_int(3);  -- Circulate inverted MSB to LSB
else
Q_int(2 downto 0) <= Q_int(3 downto 1);  -- Shift upper bits (Right Shift)
Q_int(3)          <= not Q_int(0);  -- Circulate inverted LSB to MSB
end if;
end if;

end if;
Q <= Q_int;
end process;

end jc2_top_arch;