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i need to design a parity generator which has a bidirectional serial line. This line accepts input 1 bit at a time and gives parity for 8 bits on the 9th clock cycle on the same line. I cant seem to get this right . Could some one guide me how my code should be. Here is my code so far , i just need to put parity on the bidirectional line.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity parity_gen is
 port (
     Data: inout std_logic;
     clk : in std_logic;
     rst : in std_logic
    );
end parity_gen;

architecture arc of parity_gen is
signal count : integer := 0;
signal temp : std_logic_vector(7 downto 0):="00000000"; 
signal parity : std_logic:='0';
begin
proc :process(clk) is

begin


 if clk'event and clk='1' then
  parity <= '0';

  temp(7 downto 0) <= Data & temp(7 downto 1);
  count <= count + 1;

   if count = 8 then
    parity <= temp(7) xor temp(6) xor temp(5) xor temp(4) xor temp(3) xor temp(2) xor     temp(1) xor temp(0);
    count <= 0;

  end if;



 end if;
 end process proc;

 -- data <= '1' when count = 9 else 'Z';

end arc;  

EDIT

I tried your code but did not get the expected results. so i modified my own code , but still facing a problem that i am highlighting .

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity parity_gen is
port (
Data: inout std_logic;
clk : in std_logic;
rst : in std_logic
);
end parity_gen;

architecture arc of parity_gen is
 signal count : integer;
 signal parity : std_logic;
 signal temp : std_logic_vector(7 downto 0):="00000000";
begin

proc: process (clk) is
begin
if rst = '1' then
  parity <= '0';
  count <= 0;
  temp <= (others => '0');
  --data <= 'Z';
elsif clk'event and clk = '1' then
  if count = 9 then
    count <= 1;
  else
    count <= count + 1;
    temp(7) <= data;
    temp(6 downto 0) <= temp(7 downto 1);
    parity <= parity xor data;
  end if;
 end if;
 end process proc; 
data <= parity when count = 9 else 'Z';

As you can see in the image the parity of the 8 bits recieved is given on the 9th clock cycle. Also in the 9th clock cycle temp takes data. I dont want data to be sampled in the temp reg in the 9th clock cycle . i want to maintain the same temp as 8th cycle. From the diagram we see that it is not happening in the 9th cycle, its happening afterwards.

output waveform

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5
  • \$\begingroup\$ In what way exactly is your code not working? Are you running simulations and observing internal signals? \$\endgroup\$ – Joe Hass Apr 26 '14 at 17:56
  • 1
    \$\begingroup\$ I believe your process is concurrent with your data flow statement data <= '1' when count = 9 else 'Z'. That might make data 'Z' in the proc process. Also, consider using rising_edge(clk) instead of clk'event and clk='1'. \$\endgroup\$ – rootlocus Apr 26 '14 at 18:07
  • \$\begingroup\$ @joe hass i was unbale to assign the parity to the inout line when 8 bits were recieved. when i tried doing so i was getting inout line as 'U' \$\endgroup\$ – user22348 Apr 26 '14 at 19:04
  • 1
    \$\begingroup\$ FPGAs generally do not support bi-directional internal signals. It is possible to create a bi-directional signal right at the I/O pin by selectively enabling the pin's output driver at the times the data is to leave the FPGA. However internally the data pin will have to be designed as two separate paths, one for the input side and one for the output path. \$\endgroup\$ – Michael Karas Apr 26 '14 at 20:27
  • \$\begingroup\$ yes. The IO pin will have tristate buffers controlling the direction of data flow in the io pin. I was having a problem in doing so in the code \$\endgroup\$ – user22348 Apr 27 '14 at 3:35
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You're way over-complicating things. Calculating parity on serial data just requires one XOR gate and one flip-flop, plus a counter to count the bits in each word. Rather than critiquing your existing design, let me just show you a different implementation. I'll leave it to you to work out how it works — try drawing a timing diagram that shows all of the signals. Let me know if you have trouble understanding any of this.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity parity_gen is
  port (
    Data: inout std_logic;
    clk : in std_logic;
    rst : in std_logic
  );
end parity_gen;

architecture arc of parity_gen is
  signal count : integer;
  signal parity : std_logic;
begin

  proc: process (clk) is
  begin
    if clk'event and clk='1' then
      if rst = '1' or count = 8 then
        count <= 0;
        parity <= Data;
      else
        count <= count + 1;
        parity <= parity xor Data;
      end if;
    end if;
  end process proc;

  Data <= parity when count = 8 else 'Z';

end arc;
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1
  • \$\begingroup\$ Is it that the tristate logic is always assigned using a concurrent statement outside the process ? \$\endgroup\$ – user22348 Apr 27 '14 at 3:37

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