I was looking through the microcontrollers area of Digikey and I noticed a device that i'm interested in although there is the description of "ROMLESS" in the program memory type. http://www.digikey.com/product-search/en/integrated-circuits-ics/embedded-microcontrollers/2556109?k=LPC4330

What I take away from that is that there is no flash memory internal to the chip but since it is Read-Only memory, I question that. Maybe this mean that it needs an external EEPROM to boot the program from?

So I'm not entirely sure so here I am asking:

1) What does this exactly mean


2) How would this change a design?


Actually, it's a bit of a misnomer; there is some on-chip ROM containing boot code and a small one-time-programmable (OTP) ROM for the application to use (serial numbers, configuration data, encryption keys, etc.)

But there's no on-chip nonvolatile memory for application code (it seems they wanted to use the chip area to support more SRAM instead), which means that you need to supply some other external memory (flash, SD, hard drive, etc.) to hold the application code and data. If the external device supports random addressing, you can execute code directly from it; otherwise, you can copy code into the on-chip SRAM and execute it from there.


It generally means that the device has no on-board non-volatile storage for user code. This means that the firmware must either 1) be executed directly from an external parallel device, or 2) be read into on-board RAM from an external parallel or serial device before being executed there.

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    \$\begingroup\$ It can also execute code directly from an external SPI device using the SPIFI interface. Which gives you a lot of flash for little money, and for code that needs to run fast you can copy it to the bigger internal RAM, where it runs three times faster than from internal flash. \$\endgroup\$ – starblue Apr 27 '14 at 15:45

I have used LPC4330. It does have a boot ROM but no internal Flash.

It can execute code either from the internal SRAM or from a Quad SPI Flash.

SRAM is faster, of course, and it has multiple channels which allow both internal cores (M3 and M0) to fetch instructions and data simultaneously. If you put code/data for both cores in different SRAM blocks, they won't interfere with each other.

Executing code (or fetching data) from QSPI is of course slower, although the tiny cache memory does help... especially, random access is quite slow since the address has to be loaded across SPI. But you can get a huge capacity at a low cost.

You're supposed to place critical code and data in SRAM, and use QSPI for non performance critical stuff, like graphic data for your LCD if you have one, for example. The boot ROM will execute your code from QSPI, and the runtime includes a loader which will load code/data into SRAM according to the assignments in your linker script.

And... if you want to use your own code to flash the SPI Flash chip... like write your own firmware updater instead of using the debug probe, then this code and all the libraries it uses has to run from SRAM. You can't execute code from Flash while the flash chip is in program mode.


Check this out:


Here ROMless microcontroller are used - I suspect, is due to its advantage of persistent content being less likely to be corrupted by radiation.


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