Difference between rising edge falling edge D flip flop (asynchronous reset)?

Question

I am answering a question about a D Flip-Flop with Asynchronous Reset with the reset output '0', that is set to be rising edge triggered. What i don't know is the difference between a rising edge triggered and a falling edge triggered Flip-Flop?

If possible try to provide a schematic of what this would look like. i.e., i already know the clock, data diagrams, but i don't know how the Inverters, Transmission gates, NORs and NANDs are hooked up and if there is any difference in hooking up the Clock signal. If you can, try to provide an answer in the form of this type of diagram, ->not block diagrams<-.

This here is the diagram for a falling edge D Flip-Flop, with what i'm guessing is reset output '1'? I'm not sure on the reset either. All i know is that it's negative edge triggered.

Answer 1

The only change that is required to convert your falling-edge triggered flip-flop to a rising-edge triggered flip-flop is to swap the true (non-inverted) clock and the inverted clock at the pins of your tri-state buffers and the transmission gate. For example, the center transmission gate in a rising-edge triggered flip-flop would have the true clock connected to the NMOS transistor and the inverted clock connected to the PMOS transistor.

By the way, near the middle left of your diagram you have a circled inverter that shows Q at its output and !Q at its input. That's correct...the output of the inverter just to the right of the circled inverter is !Q (Q-bar) rather than Q. If you follow the path from the D input through an inverting tristate buffer and the NOR gate you will see that the signal at the right end of the (non-inverting) transmission gate must have the same polarity as D, so that point in your circuit represents the true (non-inverted) Q value.