I am answering a question about a D Flip-Flop with Asynchronous Reset with the reset output '0', that is set to be rising edge triggered. What i don't know is the difference between a rising edge triggered and a falling edge triggered Flip-Flop?
If possible try to provide a schematic of what this would look like. i.e., i already know the clock, data diagrams, but i don't know how the Inverters, Transmission gates, NORs and NANDs are hooked up and if there is any difference in hooking up the Clock signal. If you can, try to provide an answer in the form of this type of diagram, ->not block diagrams<-.
This here is the diagram for a falling edge D Flip-Flop, with what i'm guessing is reset output '1'? I'm not sure on the reset either. All i know is that it's negative edge triggered.