# delay on cmos inverter while increasing W of nMOS and pMOS

We have one CMOS inverter and a fixed capacitance as load , for example 0.1pF . As an experiment we increase W of nMOS and pMOS and each time we increase W, we find the delay of the inverter (using spice). We notice that while increasing W, the rate of decreasing delay is dropped. Why is this happening ?

• You mean delay of charging/discharging the load capacitance? – Adel Bibi Apr 28 '14 at 19:42

I'll assume you are reffering to the charging/discharging delay. Let's take the discharge time delay. That is TpHL (H-L) trasition. This happens when you are applying Low-to High input, your Output changes from High to Low.

This is the image of a regular CMOS inventor. Now to calculate for TpHL, it is by definition the times it takes the capacitor to discharge from Q such that the output voltage changes from VDD to VDD/2. During this period, a High input is applied, therefore, the PMOS acts as an open circuit and we will only need to analyze the NMOS.

When C is fully charged "at the beginning of the discharge", the N-mos is in saturation.

Therefore; you can apply the saturation current equation. When the the output voltage reaches VDD/2, the NMOS is in linear and you have to apply the linear current equation.

Now you've calculated the currents. we find average current Iavg = (I(0) + I(at Q = Q/2) /2

Therefore; TpHL = C * (V2-V1)/2 /Idn av

Note now, increasing W will increase the current>> which will therefore decrease TpHL. In short words: Increasing the W, will increase the average current either in saturation or linear, which will increase the charging/discharging rate >> which will decrease the delay

• I know that by increasing W decreases the delay, but I asked why the rate of this (decreasing delay) becomes smaller. For example with W the delay is 2 ns, with 2W 1ns with 3W is 0.5ns with 4W is 0.46ns, 5W is 0.43ns , 6W is 0.4ns , 7W is 0.39ns. Why the rate drops ? – Adasel Pomik Apr 28 '14 at 20:30

At some point the current provided by the transistors is so large, and the capacitor is charging so fast, that other delay factors start to become significant. In your case, the rise and fall time of the input waveform could be a significant factor. This is particularly true if the voltage source that drives the inverter input is not ideal and has any series resistance, since you are increasing the input capacitance of the inverter as you increase W.

On the other hand, it may just be a matter of interpreting the data correctly. The output rise and fall time are inversely proportional to transistor width, so if you are expecting some kind of linear relationship the data will look odd.