Before beginning a larger project in Quartus II I'm trying to do the section 8.8 "FSM as an Arbiture Circuit" example from the book "Fundamentals of Digital Logic with VHDL Design 3rd ed" and I can't get Quartus to work like it's supposedly documented. The Machine State Variable which is a VHDL SIGNAL in the FSM's Architecture won't show as anything other than Undefined, even though the FSM is working fine.
Here is a screenshot of the Finite State Machine Implemented in Quartus: http://i.stack.imgur.com/XtzCn.png
The book, in a different example shows the FSM's state just fine. The Machine State is the Y variable, which is showing an ENUM like Quartus is supposed to.
I've even followed the directions provided by Altera in the below linked pdf. The directions for this are on pages 27 to 29. I've followed them exactly but that SIGNAL is still showing up as undefined no matter what. Am I missing something?