# Quartus Gives Undefined Signal For the State of a Finite State Machine. Supposed to Be Showing Enum of the State_type

Before beginning a larger project in Quartus II I'm trying to do the section 8.8 "FSM as an Arbiture Circuit" example from the book "Fundamentals of Digital Logic with VHDL Design 3rd ed" and I can't get Quartus to work like it's supposedly documented. The Machine State Variable which is a VHDL SIGNAL in the FSM's Architecture won't show as anything other than Undefined, even though the FSM is working fine.

Here is a screenshot of the Finite State Machine Implemented in Quartus: http://i.stack.imgur.com/XtzCn.png

The book, in a different example shows the FSM's state just fine. The Machine State is the Y variable, which is showing an ENUM like Quartus is supposed to.

I've even followed the directions provided by Altera in the below linked pdf. The directions for this are on pages 27 to 29. I've followed them exactly but that SIGNAL is still showing up as undefined no matter what. Am I missing something?
ftp://ftp.altera.com/up/pub/Altera_Material/11.0/Tutorials/VHDL/Quartus_II_Simulation.pdf

• Fig 29 on Page 28 shows Type MACHINE, Value Type Enum, we can see the Radix in your desktop display. Your State Table Encoding tab shows you've renamed Idle to gnt0, which shows up in the source. You've also renamed Y (from the bookP to state. If it were me I'd re-insert the Bus state and make sure the selections match Fig 29. – user8352 Apr 29 '14 at 6:36
• Initially everything was exactly the same. Everything you mentioned that doesn't match was changed while I was literally trying everything. – Derek Ziemba Apr 30 '14 at 8:00

This is definitely a Quartus II issue. I'd suggest you you delete state from the simulation display and re-add it insuring it matches Figure 29 on Page 29 of the tutorial you provided the link for, above.

I wrote a test bench that reproduces the waveform from the book. You can use it to insure the arbiter works as intended even if you can't display state:

library ieee;
use ieee.std_logic_1164.all;

entity arbiter_tb is
end entity;

architecture foo of arbiter_tb is
signal clk:        std_logic := '0';
signal reset:      std_logic := '0';
signal r:          std_logic_vector(1 to 3) := (others => '0');
signal g:          std_logic_vector(1 to 3);
begin
CLOCK:
process
begin
wait for 50 ns;
clk <= not clk;
if Now > 1150 ns then
wait;
end if;
end process;

DUT:
entity work.arbiter
port map (
clk => clk,
reset => reset,
r => r,
g => g
);

STIMULUS:
process
begin
wait for 51 ns;
reset <= '1';
r <= (others => '1');
wait until rising_edge(clk) and g(1) = '1';
r(1) <= '0';
wait until rising_edge(clk) and g(2) = '1';
r(2) <= '0';
wait until rising_edge(clk) and g(3) = '1';
r(3) <= '0';
wait;
end process;

end architecture;


And this is as close as I could get with ghdl and gtkwave:

If re-adding state didn't work you'll need to find Altera specific help.

Figured it out. In the Waveform editor, go to Options, then change the Simulator from ModelSim to Quartus II Simulator.