You will not get a cheaper layer stack-up by routing higher impedance traces unless you have a lot of room on the board. If you do have too much room on the board, consider reducing the board area instead (with PCB's you basically pay for area). But first of all make sure you have a sufficiently high production volume for this to be a good trade for the time you put into it.
As an example: With a typical western world setup, you need maybe 10K/yr volumes for the total cost of reducing layers from 10 to 8 to pay off.
If what you are building is a simple point-to-point connection between controller and a solder-down memory, the solutions you have are not very attractive:
1) Keeping the stackup, changing the trace width
50R stripline example: 17um Cu, 0.9mm to both reference planes, 0.69mm trace width.
To change this to 100R keeping the stackup would mean going to a 0.1mm trace.
In this case crosstalk would be comparable, but you waste area on the wider traces.
2) Changing the stackup, keeping the trace width
50R stripline example: 17um Cu, 0.15mm to both reference planes, 0.1mm trace width.
To change this to 100R keeping the trace width would mean going to 0.9mm to both reference planes.
In that case spacing would need to change for the same crosstalk, and you waste area again.
None of the very thick stackups are practical anyways.