I've worked with DDR2 and DDR3 memories and usually stuck to 50 ohm impedance for traces. But i do see that SoCs and DDR2/3 memories seem to support other impedances such as 30, 60 and 150 ohms.

Now if using other impedances allows for a cheaper layer stackup then i guess i should have the option of going for it as long as i'm willing to accept the downsides of higher or lower impedances regarding EMC suspectibility and radiation.

Are there any other specific downsides to this ?


There are no real downsides to any impedance for EMI, as long as you have matched impedances on source, termination and trace.

One thing that many fail to consider is the typical routing of DDR2/3 with a data line that goes far enough from the CPU to be considered a transmission line, then T's to go to each chip (or 4 chips, etc.) The 50 ohm impedance just dropped to 25 ohm, with two traces in parallel. This creates an impedance mismatch, which always creates a reflected signal and noise on the line.

The proper way to handle this is to T the lines either close enough to the CPU to still be considered a lumped length, with a series termination at the T of 1/2 the line impedance. The signal sees 25 ohm resistor to a 25 ohm parallel set of 50 ohm transmission lines and everything is good. Or this can be done where the T's will be short enough to be considered lumped at the two RAM chips.

A similar setup can be used to match impedances differing CPU to RAM, but it is best to keep SoC and RAM source and termination impedances the same, then make traces to match.

If you have differing impedance only at the RAM side, you should be able to use parallel or series termination resistors to match to that.

  • \$\begingroup\$ Application notes mention that lowering the impedance results in higher di/dt which may increase radiation, similarly increasing it will make the lines more susceptible to interference. That is what i meant by EMI (not signal integrity) \$\endgroup\$ – Steinar Apr 29 '14 at 12:01
  • \$\begingroup\$ Ah, I was looking at it in the generating sense, rather than receiving sense. \$\endgroup\$ – Joe Apr 29 '14 at 12:11
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    \$\begingroup\$ Just to get some facts straight: DDR2 is designed for the T-routing of CA (Command-Address) lines, whereas DDR3 is designed for fly-by routing of CA. DDR2 is designed with ODT (on-die termination) on DQ/DQS/DM lines, whereas DDR3 has dynamic ODT. \$\endgroup\$ – Rolf Ostergaard Apr 30 '14 at 5:52
  • \$\begingroup\$ @Steinar: You do not get significant radiated EMI from PCB traces. So you may trying to fix a problem that is not there to begin with. \$\endgroup\$ – Rolf Ostergaard Apr 30 '14 at 5:55
  • \$\begingroup\$ Actually i'm not chasing lower radiated EMI. It's more exploring ways to increase my layer stackup choices. But as you already mentioned increased crosstalk is seen with higher distance to the reference plane. But exploring my options doesn't hurt though \$\endgroup\$ – Steinar Apr 30 '14 at 11:30

You will not get a cheaper layer stack-up by routing higher impedance traces unless you have a lot of room on the board. If you do have too much room on the board, consider reducing the board area instead (with PCB's you basically pay for area). But first of all make sure you have a sufficiently high production volume for this to be a good trade for the time you put into it.

As an example: With a typical western world setup, you need maybe 10K/yr volumes for the total cost of reducing layers from 10 to 8 to pay off.

If what you are building is a simple point-to-point connection between controller and a solder-down memory, the solutions you have are not very attractive:

1) Keeping the stackup, changing the trace width

50R stripline example: 17um Cu, 0.9mm to both reference planes, 0.69mm trace width. To change this to 100R keeping the stackup would mean going to a 0.1mm trace.

In this case crosstalk would be comparable, but you waste area on the wider traces.

2) Changing the stackup, keeping the trace width

50R stripline example: 17um Cu, 0.15mm to both reference planes, 0.1mm trace width. To change this to 100R keeping the trace width would mean going to 0.9mm to both reference planes.

In that case spacing would need to change for the same crosstalk, and you waste area again.

None of the very thick stackups are practical anyways.


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