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Quoting answer from thread "Using signal in different modules vhdl":

if one drives '1' and the other '0' at the same time, you have created a short circuit across the power supply, and you can potentially damage the device.

Is the damage really possible? I'd think there would exist some sort of protections inside the chip.

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  • \$\begingroup\$ Why would you think that? These chips are designed for performance, after taking into account all of the other constraints the designers face. Adding "protection" circuitry would just slow things down. \$\endgroup\$
    – Dave Tweed
    Apr 29, 2014 at 16:26

2 Answers 2

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I don't think it is possible to drive a pin high and low at the same time. In the schematic below, there is only one output driver for the I/O block (IOB). Also, as far as I know, there is no protection against shorts inside the chip. However, according to Austin Lesea, a Xilinx engineer, in this thread, shorting a pin driven high to ground should not damage the output circuitry: "In the past, IOs could get shorted to Vcc, or ground, for months, and not degrade (as long as the die temperature remained below 125C). Of course, we do not suggest you abuse your parts this way."

This is particularly true if the output circuit is limited to one of the lower drive values. The Spartan-3 IOB's, for example, can be programmed to output up to 2, 4, 6, 8, 12 or 16 mA -- see page of this datasheet.

enter image description here

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    \$\begingroup\$ External logic can supply a second source of drive current. Damage may be potential rather than actual - your Xilinx reference provides some sort of guarantee that damage won't occur, with caveats about die temperature (due in part to excessive I/O consumption?) \$\endgroup\$
    – user16324
    Apr 29, 2014 at 20:30
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Are you talking about within the FPGA or outside the FPGA?

Inside the FPGA, the tools will not let you have two signals driving the same wire such that they could 'compete'. If you use VHDL and std_logic signals, then you can get the tools to infer a multiplexer which will make it appear like multiple signals are driving, but the logic will ensure that only one signal actually makes it through to drive the destination signal.

Outside the FPGA, yes, if two devices (or pins of the same device I guess) are driving the same signal they will act as a low resistance path across the power supplies. This will create a long-term reliability issue for the pins in question as they are not designed to pass the largish currents that will flow for long periods of time. However, it is not a recipe for instant catastrophic failure in my experience.

An answer from Austin Lesea (who works for Xilinx and knows the chips inside out):

As long as you stay within the Absoulte Maximum (Table 1, section 3) limits of the specifications for any currents and voltages, everything will be just fine.

Shorting an IO pin to ground momentarily will not damage the device. Shorting it for months just might damage it.

Shorting more than one pin to ground momentarily will also not damage the device.

Shorting ten or more to ground for a long time just might damage the device.

Driving an output pin with another chip is likely to damage the other chip, not the FPGA.

(From http://www.fpgarelated.com/comp.arch.fpga/thread/15911/io-pins-short-circuit-protection.php)

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