I'm trying to load configuration to my FPGA board using Cypress FX2LP from USB. The basic implementation comes from Cypress's AN63620 application note, but instead Spartan 3 I use Spartan 6 (xc6slx4), and the pin layout is different for control signals. I use 8 bit bus for configuration, but because it was easier to route they are mixed from some bits on Cypress's 0-7 and 8-15 data buses. I modified the Cypress's source to load 16 bit words and wrote a host application that shuffles bits in the correct order. I checked the bus with logic analyzer, and everything seems to be fine, I can clearly see the startup sequence (0xAA 0x99 0x55 0x66 in correct bit order).

My problem is that the FPGA doesn't even starts the configuration. I think this because if I read the status register, everything is the same just as after the reset by PROG_B, every error bit is 0. I even tried to send a corrupted stream with correct start sequnece to see if I can get any error bits 1 (mainly CRC error), but I cant. They always stay 0.

I can program the FPGA with JTAG and my hello world led blinking application works (clocked from CCLK) so the FPGA should not be damaged physically. I measured all the supply voltages, they are all correct, with very little noise.

From the status register read I can see that M1=1 and M0=0, which is the correct setting for SelectMAP Slave.

I read a sentence in Spartan 6's configuration guide that I can't find in Spartan 3's: "Prior to sync word detection, the D[0:n] pins are sampled on every clock edge regardless of the state of CSI_B". Does this mean that the subsequent bytes of the synchronization word must be put on the bus on immediately after each other and it can't be paused by CSI_B? If this is the case, the GPIF interface can't be used to load the configuration (because it takes many clock cycles per byte, and the loading is gated by CSI_B). Maybe only the sequence matters, and not the timing of the sync word?

I cannot even find any example of anyone trying to configure a Spartan 6 with Cypress and SelectMAP Slave.

What could be the problem? Maybe some signal integrity problems that doesn't matters for the analyzer but for the FPGA it does?

EDIT: I solved the problem by cutting the clock line and connecting it to a GPIO of the Cypress, tied CSI_B to ground and bitbanged the same bitstream in on every single rising clock edge.

  • \$\begingroup\$ Well, without knowing how you connected the FPGA and the controller, it is hard to guess where the problem is. If you share your schematic of netlist and/or the code you are using to program the FPGA, we might be able to help you. \$\endgroup\$ – FarhadA Apr 30 '14 at 8:29
  • \$\begingroup\$ You can download the KiCad project from almafa.org/xdever/sdr_kicad.zip \$\endgroup\$ – xdever Apr 30 '14 at 8:41
  • \$\begingroup\$ The schmatic in PDF format: almafa.org/xdever/fpga_board.pdf \$\endgroup\$ – xdever Apr 30 '14 at 9:43

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