I am using a Spartan 6 xilinx FPGA, I managed to get it all working, changing the multiplier and divisor parameters at runtime. DCM_CLKGEN I use.
My real oscillator is 66.6 MHz, but with PLL_BASE, I can change it. As we need a clock frequency from 1 to 100MHz, I am wondering, what base frequency would I take? I set it to 40MHz, just to choose something, that seemed nice....
FREQUENCYout = FREQUENCYbase * MULTIPLIER / DIVISOR
I made a simple spreadsheet to see how different multipliers and divisors convert the base frequency, some divisors on the column headers, some multipliers on each row, so I get a matrix of possible outcome frequencies. Although not for every frequency (It would get bulky). I can't believe trial and error is the way to define those parameters, but surprisingly, I don't find much information on the net about it.
The divisor and multiplier have to be integers (no floating points), otherwise I could just choose "any" multiplier, and calculate a divisor, by completing the equitation.
- question 1: base frequency for a wide range of output frequencies.
- question 2: a general way of working for defining the multiplier and divisor.