0
\$\begingroup\$

I know VHDL and I understand the syntax but I never programmed an FPGA before. I am going to write soon my first VHDL code and then upload my code to Xilinx FPGA. When writing VHDL code we have entity. On the examples I saw, signals in UCF file are always related to the top level file not others. Is this correct? Because when I write my own code, Im confused about mapping which signal to which file, vector signals and their differences from others and how the files are connected with each other etc. Since this is not Java/Cpp I feel really weak. Is there a tutorial/link which can give me a fine start for my first project?

I know what clock divider is, it divides the clock ... but why dont we use the system clock 50 Mhz for example? What is clock divider good for? What is the advantage? Do we need it at all? How do I use clock divider in my codes?

\$\endgroup\$
2
\$\begingroup\$

Xilinx UCF is a constraints file format. It is used to apply various constraints on the design to the Xilinx tools, including but not limited to pin locations, timing, and area. When mapping your RTL (VHDL) design to a physical device, you will minimally need clocks and pin constraints at the top level, but constraints for real designs can go much further than this. Xilinx has a User Constraints Guide on this subject.

You can use the system clock if it meets your needs. Very often, real designs require clocks at a specific (lower) frequency, or multiple clocks at different frequencies, which is where clock dividers would be used.

A gentle dead tree introduction to VHDL programming for Xilinx I can recommend is this book. I recommended a book, since I have not found online HDL tutorials nearly as concise or complete as those for software. You should also scour Xilinx's online documentation for their tools and the part(s) you're using.

\$\endgroup\$
1
\$\begingroup\$

The UCF file usually (I have never seen done it in other ways) refers to signals in your top file. In this top file, then, you can instantiate other VHDL files that are in your project.

As for the clock divider, in many applications you need to get lower clocks (e.g. you need to interface with a slower external device).

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.