I know VHDL and I understand the syntax but I never programmed an FPGA before. I am going to write soon my first VHDL code and then upload my code to Xilinx FPGA. When writing VHDL code we have entity. On the examples I saw, signals in UCF file are always related to the top level file not others. Is this correct? Because when I write my own code, Im confused about mapping which signal to which file, vector signals and their differences from others and how the files are connected with each other etc. Since this is not Java/Cpp I feel really weak. Is there a tutorial/link which can give me a fine start for my first project?
I know what clock divider is, it divides the clock ... but why dont we use the system clock 50 Mhz for example? What is clock divider good for? What is the advantage? Do we need it at all? How do I use clock divider in my codes?