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I am trying to understand how regulation happens on Cycle-Cycle basis in the case of Voltage Mode Control (VMC) and Current Mode Control (CMC).

I understand that in the case of VMC, an error amplifier compares Vout of the power supply with a fixed reference (Vref) and generates an error output Vc. It is this Vc which then compared with a sawtooth waveform of fixed frequency resulting in PWM of varying duty cycle. To cut a long story short, Vc influences the duty cycle.

What exactly is the nature of Vc and how does it change?

Lets imagine that a power supply has Vin = 12V and Vout = 3V. Designer has wished that Vc = 1V when Vout = 3V. Yes, we are discussing a text-book buck.

Imagine the case when the load increases resulting in Vout falling to 2.1V. Vc must therefore rise. When Vc rises to e.g 1.5V, the duty cycle increases and consequently Vout rises again to 3V.

With Vout rising again to 3V, what will be the value of Vc now? Will it stay at 1.5V or will it fall back to 1V?

If Vc fell back to 1V, then Vout will always be hovering between 2.1V and 3V? Is this correct understanding? Is this the reason why VMC is deemed unsuitable for large load changes?

There is a compensation network on the output of op-amp error amplifier. What does it do?

I apologize but Kindly strive not to explain in terms of poles/zeroes, bode-plots, control theory, transfer functions etc. I have not reached a stage where I would be able to appreciate them.

My next question on CMC will follow once I have a better understanding of VMC.

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It's hard to explain a control system without control theory, but Vc will typically be the output of the compensator, which is the error signal modified by the compensation.

This goes into a modulator. So this voltage basically "sets" the duty cycle of the PWM. So working backwards, whatever the output voltage is requires a certain duty cycle. In the case of a buck converter (in CCM) it's Vout/Vin. Drawing current from the output would normally cause the output to drop due to series impedances, but the control loop will adjust the duty cycle by moving Vc up slightly to keep the output at a constant value.

The compensation adjusts the response of the controller so that Vc gets to just the right point in a reasonable amount of time without overshooting the mark or oscillating.

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  • \$\begingroup\$ So in my original example, Vc stays at 1.5v provided Vout == VRef. So the compensation network "maintains" Vc once Vout - Vref = 0. Correct? \$\endgroup\$ – Raj May 3 '14 at 4:53
  • \$\begingroup\$ Correct, Vc will stay at whatever value it needs to be in order to keep the output at Vref. If the load goes away, it will drop back down (assuming down=lower duty cycle) and stay where it was prior to the load being applied. \$\endgroup\$ – John D May 3 '14 at 5:10
  • \$\begingroup\$ Thanks so much. This was one of my key misunderstandings and you have clarified it. Thanks so much again! \$\endgroup\$ – Raj May 3 '14 at 5:15
  • \$\begingroup\$ Follow up question: Once there is a change in Vout, can it take several PWM cycles before the compensation network generates an updated Vc? Is that the reason why Voltage mode is considered slow? \$\endgroup\$ – Raj May 3 '14 at 5:18
  • \$\begingroup\$ Well, I would say that it could take several cycles until Vc reaches its final value, though it should start reacting to a change immediately. If the compensation is designed properly, voltage mode doesn't have to be slow, it can be very competitive with current mode- It's just that compensating it for high performance can be much harder. \$\endgroup\$ – John D May 3 '14 at 13:40

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