I am trying to understand how regulation happens on Cycle-Cycle basis in the case of Voltage Mode Control (VMC) and Current Mode Control (CMC).
I understand that in the case of VMC, an error amplifier compares Vout of the power supply with a fixed reference (Vref) and generates an error output Vc. It is this Vc which then compared with a sawtooth waveform of fixed frequency resulting in PWM of varying duty cycle. To cut a long story short, Vc influences the duty cycle.
What exactly is the nature of Vc and how does it change?
Lets imagine that a power supply has Vin = 12V and Vout = 3V. Designer has wished that Vc = 1V when Vout = 3V. Yes, we are discussing a text-book buck.
Imagine the case when the load increases resulting in Vout falling to 2.1V. Vc must therefore rise. When Vc rises to e.g 1.5V, the duty cycle increases and consequently Vout rises again to 3V.
With Vout rising again to 3V, what will be the value of Vc now? Will it stay at 1.5V or will it fall back to 1V?
If Vc fell back to 1V, then Vout will always be hovering between 2.1V and 3V? Is this correct understanding? Is this the reason why VMC is deemed unsuitable for large load changes?
There is a compensation network on the output of op-amp error amplifier. What does it do?
I apologize but Kindly strive not to explain in terms of poles/zeroes, bode-plots, control theory, transfer functions etc. I have not reached a stage where I would be able to appreciate them.
My next question on CMC will follow once I have a better understanding of VMC.