D flip flop using transmission gates

Question

In this circuit when D=0 and Clk=0 the value passes from w-x-y-z and z= 1. So at z= not D So this path constitutes what is called setup time of the flip flop. But at the same time the value at D can also move to the slave flip flop is'nt it ? As when clk=0 the 3rd transmission gates pmos will be on and it will be able to pass the zero at x . So how is the master slave action taking place. Is it that the 3rd transmission gates pmos cannot pass a strong 0 so it gets ignored ? If that is the case if i remove the inverter at input ill get a 1 , and so it will pass that strong 1. Please someone explain me this operation without ignoring the second slave latch when master is receiving input

Answer 1

When the clock is low, X follows whatever value D has continuously. However, M is isolated from X, and so Q holds whatever value is stored in the slave FF.

When the clock is high, W is isolated from D, but now M is connected to X, so now the value on X is transferred to Q.

There's a critical moment as the clock goes from low to high at which X stops following D. If D is changing at this time, it's impossible to predict what value X will end up with — it could even become metastable. There's a certain amount of time starting before the rising edge of the clock and ending some time afterward, during which D must be stable in order to guarantee that its value is correctly transferred to Q; these are called "setup" and "hold" time, respectively.

Note that since the two transmission gates in the top row are never "on" at the same time, there's no way that D can ever directly affect the value of Q.

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