I was going through Mano's "Computer architecture " , in chapter memory organization they have used a RAM chip with 2 chip select pins CS1 and CS2' but i can't think of the reason why , all the chip select features can also be implemented by using only one chip select pin and READ/WRITE pins according to . Why do we need two chip select pins (CS1 and CS2') here ?

Here is the link to the page in the book(pg no 451). enter image description here

thanks .

  • 2
    \$\begingroup\$ It's been ages since I've seen a chip with two CS lines but I seem to recall it was mainly a convenience so for example one could be connected to an address decoder while the other side was connected to the CPU. So the memory would only take over the bus when the address matched and the CPU was requesting memory access. \$\endgroup\$ – PeterJ May 4 '14 at 6:44

Chip select lines are usually asserted low, e.g. !CS (where ! represents the bar over the name). For this reason, address decoders like the 74HCT138 output a 0 on the decoded address line.

But sometimes, an address select line may be generated from some logic such that it is asserted high instead of low. If there are extra pins available on a package, rather than leaving the pin as NC (no connect), the designer of the chip may include a second chip select of the opposite polarity.

Both the CS1 and !CS2 lines are not necessarily used together.

If the address line is asserted low, then the designer using the chip can run the line into !CS2, and tie CS1 high

enter image description here

If the address line is asserted high, the designer using the chip can run the line to the CS1 line and tie !CS2 low. This saves an extra inverter in the circuit which would have been needed if the only chip select was !CS.

enter image description here

Other times, it may be convenient to use both teh CS1 and !CS2 lines together. Note in the datasheet for the 74HCT138 chip mentioned above, it actually provides three enable lines (like chip selects), G1, !G2A and !G2B, which are all anded together. Again, the logic designer may elect to use only the low asserted or high asserted line(s), and tie the opposite high or low as described above, or they make have some more elaborate logic that makes use of two or all three of the enable lines.


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