PCIe connections have one to two ground contacts per differential signal pair. Why is this the case?

On the boards that I have been studying, all of these pins are tied together onto the same ground plane on the board (at least as far as I can tell), so does it really make a difference? They should all be at essentially the same potential, right?

Are there just ground pins interleaved with the signal pairs in order to absorb any potential crosstalk between adjacent pairs? If this is the case, why are you supposed to remove any (internal) ground plane in the contact area?

  • 3
    \$\begingroup\$ Have you studied transmission line theory? \$\endgroup\$
    – Samuel
    May 6 '14 at 6:20
  • 1
    \$\begingroup\$ This is a very broad topic and I suspect it is far beyond a single answer. You'd be better off studying on your own. \$\endgroup\$
    – Dzarda
    May 6 '14 at 7:34
  • \$\begingroup\$ Its all about signal integrity and emitted noise. Study transmission lines, you'll get it. \$\endgroup\$
    – Funkyguy
    May 6 '14 at 14:04

Ok, so I think that I have at least some idea now:

  • Considering the 100 MHz signaling frequency, the data and clock signals need to run over transmission lines (assuming a propagation speed through copper of 0.6c, the wavelength is ~1.8m, and using the 10% wavelength rule of thumb and the fact that there is probably higher frequency content in that 100 MHz base signal, it's right in that range).
  • In order to minimize signal reflections and other distortions in the line, impedance needs to be as consistent as possible throughout the line. At the frequencies that make it a transmission line, the impedance of the line is dominated by reactance, and more specifically, by the ratio of inductance to capacitance.
  • I'm assuming that the inductance of a trace on the PCB will be largely constant for a given length regardless of the layout (excepting funky routing), so the impedance has to be controlled by adjusting the capacitance, which is managed by moving the signal lines closer to or further from the ground plane and/or traces.
  • The ground plane is absent under the card edge for three reasons:
    1. The signal pins are wider than the traces, which would result in a higher capacitance between them and the ground plane.
    2. The ground pins add capacitance to the line.
    3. The PCIe connector is built to have the proper impedance as-is, and placing a large ground plane right in the middle would throw off the capacitance, and therefore the impedance.
  • I think that the ground pins between the signal pins probably help to reduce crosstalk, but maybe that is a secondary concern?

Am I anywhere close to the right answer, or am I way off? I had looked at transmission lines multiple times and couldn't figure it out, but this answer kind of just came to me after paying more attention to the formula for determining characteristic impedance.

  • \$\begingroup\$ GND wires interleaved with the signal lines to reduce the effects of capacitive coupling between neighboring signal wires (reducing crosstalk) was also used for Parallel ATA cables. Thats why they introduced the 80 pin version (original 40 pin). \$\endgroup\$
    – Rev
    Aug 26 '14 at 7:17
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    \$\begingroup\$ @Rev1.0 Not 80-pin, 80-wires. Those cables still had only 40 pins. \$\endgroup\$ Dec 3 '15 at 11:33
  • \$\begingroup\$ @DmitryGrigoryev: That is of course correct. \$\endgroup\$
    – Rev
    Dec 3 '15 at 13:13
  • \$\begingroup\$ The signaling rate of PCI express is not 100 MHz, PCIe gen 1 is 2.5 Gbps per lane, and newer versions are much faster. But yes, this is entirely about signal integrity along all of the differential pairs, minimizing both reflections and crosstalk. \$\endgroup\$ Jun 9 at 7:46

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