# How can I minimize the variance in voltage drop across transistors - or eliminate transistors from this design?

I have a fairly simple circuit that I'm using with an arduino to measure the impedance on a very low-resistance circuit. The user plugs in a device at A and B and the arduino can compute the resistance across the user's device by measuring the voltage at A. No resistance on the user device means I read 0V, infinite resistance means I see about 1 volt. The most common user device will register about 1 Ohm. (For the sake of anyone familiar with arduino, I use the internal voltage reference so that 1V reads near the max for analogRead.)

+5V
|
z
z 220 Ohm Resistor (.1% tolerance)
z
|
A----------------------------------------\
|                                        |
z                                        |
z 47 Ohm Resistor (.1% tolerance)        |
z                                        |
|                                        |
|                                        |
GND---------------------------------------B


The trouble is that the circuit has to measure multiple user devices at the same time. I can't just replicate this chunk of circuit 3 times because changes on any one of the user devices will affect the values read on the other arduino input pins.

My solution to this was to put a transistor between 5V and the first resistor and compensate for the voltage drop across the transistor by choosing a smaller resistor. This makes the circuit look like this:

+5V
|    (Worst ASCII art transistor ever)
\
\|   1K Ohm
|-----NNN---- (To Arduino Pin to select this channel.)
/|
/
v
|
|
z
z 150 Ohm Resistor (.1% tolerance)
z
|
A----------------------------------------\
|                                        |
z                                        |
z 47 Ohm Resistor (.1% tolerance)        |
z                                        |
|                                        |
|                                        |
GND---------------------------------------B


This circuit gets replicated once for each user input. This works, but my input values are unpredictable because the voltage drops across the transistors isn't consistent. (A measurement of 27 on one channel might equal a 2 Ohm user device, while that same device on a different channel might read 47. A 10% jitter I could tolerate. Greater than 60% renders the project unusable.)

I don't think that I can get transistors that will be in the neighborhood of .1% tolerance without paying a fortune (assuming I can get them at all.)

Because the math is being done on the arduino, I can't easily take 3 measurements (using the transistor-free design) and solve the simultaneous system of equations fast enough. (I'm looking at 500 to 1000 measurements of all three channels every second.)

Is there any way to salvage the project?

• Welcome back. FYI. We now have a CircuitLab schematic editor on EE.SE. There is a Schematic button on the toolbar, when you edit the question. So, no need to do the ASCII art, unless you like it. – Nick Alexeev May 8 '14 at 21:11

No, I don't think you are looking at this correctly at all. If your 5V is stable then there is nothing wrong with your method using fixed resistors and no transistors. The problem is that each ADC input on your MCU has a different error voltage. Check out the dc offset error potential in the data sheet. Here is a typical example from maxim covering the offset error on ADCs and DACs: - Around 0V, the error could be +/-50mV. In a perfect system, a 1 ohm resistor fed from 5V via a 150 ohm resistor produces a voltage of 33mV - you got a digital value of 27 and, assuming your ADC is 10-bit then 27 represents 132 mV - how do you rationalize this? Forgive me if it isn't a 10-bit ADC but, if it were 12 bits then 27 represents 32.9mV (possibly coincidentally of course) but 47 represents 57mV!!! Assuming they are all 1 ohm resistors and accurately matched (or you used the same resistor on a different channel) you have to conclude you are witnessing ADC offset error in action.

You don't show what kind of transistor (NPN Or PNP) you're using, but the implied 1.75V drop makes me think it's an NPN emitter follower.

You want a high-side saturated switch. You could use a P-channel logic-level MOSFET or you could use a PNP transistor such as a 2N4403/MMBT4403 with maybe a 1K base resistor. The 3mA or so base current will give you a saturation voltage of about 85mV that should be consistent within about 20%, so that's a variation of about +/-0.3% in current. With a MOSFET you can easily get down to 0.1% by choosing a logic-level p-channel MOSFET with an Rds(on) of less than 200m$\Omega$ over temperature.

In both cases, low = 'ON' so you'll need to reverse the logic.

Use a P-channel FET with an RDSon that is very small compared to your resistor values. If this isn't for production you could even use a device with a few mOhms of on resistance.

• Curious, what does "for production" or not affect whether the OP can use a FET with a mOhm(s) resistance? – tcrosley May 9 '14 at 2:47
• @tcrosley It's just that it's overkill. They will be larger and more expensive than necessary for the function, but if it's a one-off type of thing it removes the need to optimize price/performance. – John D May 9 '14 at 3:34

replace point 'v' with a resistor and then a zener to ground that makes a new voltage reference (lower than 5v) - you'll lose just under 2v in the switching transistor so chooses a resistor that leaves a voltage just a bit above 3V (so the zener kicks in) maybe something in/around 30ohms or so (play a bit, it depends on the transistor you choose)