0
\$\begingroup\$

For example if i am going to model T flip flop using D flip flop. I am not writing the whole code of T flip flop as here it is not related to my query.

module T_ff(q,clk,clear);            
//...............   
//Instantiate the D flip flop          
D_ff dff(q,~q,clk,clear);            
endmodule  


// edge triggered D flip flop             
module D_ff(q,qbar,d,clk,clear);             
//..............                                    
endmodule   

The number of input/output ports are different in Instantiate of D flip flop (define inside the T flip flop) and in module of D flip flop. Is it fine? Can it result in error?

\$\endgroup\$
1
  • 2
    \$\begingroup\$ These are port connections not parameters. Parameters are declared with parameter or localparam. \$\endgroup\$ – pre_randomize May 10 '14 at 6:51
5
\$\begingroup\$

When using Port Order connections, the ports are connected in the order declared by the module, and any unused ports are left unconnected (Z).

Instantiating by Port Name connections helps avoid this kind of problem.

Your code is interpreted as this:

D_ff dff_instance (  
        .q     ( q     ), // first port
        .qbar  ( ~q    ), // second port
        .d     ( clk   ), // third port
        .clk   ( clear ), // fourth port
        .clear ( 1'bZ  )  // fitfh port has no connection
    );

Clearly what you intended was this:

D_ff dff_instance (  
        .q     ( q     ),
        .qbar  (       ),  // unconnected output
        .d     ( ~q    ),  // toggle by driving dff_instance.d input from ~q
        .clk   ( clk   ),
        .clear ( clear )
    );

If you are using an older verilog compiler that does not support Port Name connections, skip the unused port by two commas:

D_ff dff_instance ( q, , ~q , clk, clear); // qbar output port is unconnected

The Port Name connection style does require more typing, but makes the code easier for a person to read and understand, and more robust against connection errors.

\$\endgroup\$
2
  • \$\begingroup\$ Just at a curiosity, what older verilog compiler does not support port name connections? It would have to be before the first IEEE verilog standard or it will be non-compliant with IEEE 1364-1995 § 12.3.4 Connecting module ports by name. \$\endgroup\$ – Greg May 12 '14 at 17:10
  • \$\begingroup\$ You're right, any modern verilog compiler should accept connecting ports by name. Sometimes student example code uses port order connections, which isn't as clear in my opinion. As soon as I learned how to enable Xilinx ISE 12 to use Verilog-2001, I started coding this way and haven't looked back. \$\endgroup\$ – MarkU May 13 '14 at 3:25

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.