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I'm Getting warnings while synthesing the below code. Tried many ways but in vain. Can anyone please suggest what might have gone wrong with my code. The code is to latch the data as and when the corresponding ring counter values become one. I've just started learning HDL coding !..

entity PLowLatch is
  Port ( 
    ppOut_MUX1    : in   STD_LOGIC;
    ring          : in   STD_LOGIC_VECTOR (3 downto 0);
    PlowLatch_out : out  STD_LOGIC_VECTOR (3 downto 0)
  );
end PLowLatch;

architecture Behavioral of PLowLatch is
begin

  process (ring, ppOut_MUX1) begin
    if (ring(0) = '1') then
      PlowLatch_out(0) <= ppOut_MUX1;
    elsif (ring(1) = '1') then
      PlowLatch_out(1) <= ppOut_MUX1;
    elsif (ring(2) = '1') then
      PlowLatch_out(2) <= ppOut_MUX1;
    elsif (ring(3) = '1') then
      PlowLatch_out(3) <= ppOut_MUX1;
    else
      PlowLatch_out <= "0000";
    end if;
  end process;

end Behavioral;

Below is the warning

WARNING:Xst:737 - Found 1-bit latch for signal <PlowLatch_out_0>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <PlowLatch_out_1>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <PlowLatch_out_2>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <PlowLatch_out_3>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
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  • \$\begingroup\$ If you got a VHDL'93 compiant compiler did you try PlowLatch_out <= ('3' => ppOut_MUX1, others => 0);? \$\endgroup\$ – drahnr May 11 '14 at 18:08
  • \$\begingroup\$ May I know as to what exactly the code suggested by you does? \$\endgroup\$ – user40295 May 11 '14 at 18:11
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Whenever you have an asynchronous process that doesn't make an assignment to every output variable in every possible path through the code, you create an implicit asynchronous latch for each variable not assigned. This is what the warnings are about: Each of your PlowLatch_out variables is only assigned in one branch of your if-then-else structure, so a latch is created for each one.

It's possible that this is what you intended, but the problem is that this is a poor design approach for FPGAs. In general, the logic fabric of an FPGA is not fully characterized with regard to the performance of asynchronous state machines (including basic latches), and the design tools go to great lengths to encourage to to make your design synchronous (i.e., with a clock).

You should bring the same clock that drives the ring counter into this module, something like this:

entity PLowLatch is
  Port ( 
    clock         : in   STD_LOGIC;
    ppOut_MUX1    : in   STD_LOGIC;
    ring          : in   STD_LOGIC_VECTOR (3 downto 0);
    PlowLatch_out : out  STD_LOGIC_VECTOR (3 downto 0)
  );
end PLowLatch;

architecture Behavioral of PLowLatch is
begin

  process (clock) begin
    if rising_edge(clock) then
      if (ring(0) = '1') then
        PlowLatch_out(0) <= ppOut_MUX1;
      elsif (ring(1) = '1') then
        PlowLatch_out(1) <= ppOut_MUX1;
      elsif (ring(2) = '1') then
        PlowLatch_out(2) <= ppOut_MUX1;
      elsif (ring(3) = '1') then
        PlowLatch_out(3) <= ppOut_MUX1;
      else
        PlowLatch_out <= "0000";
      end if;
    end if;
  end process;

end Behavioral;
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  • \$\begingroup\$ Oh okay!..Thanks for the inputs. So after making the design synchronous it should work!. \$\endgroup\$ – user40295 May 11 '14 at 18:30
  • \$\begingroup\$ Yes, it'll work now. \$\endgroup\$ – user40295 May 11 '14 at 18:36

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