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As I understand it, digital multiplexers contain multiple inputs (2^N), one output, and N selector lines. The selector lines are used to select which input is mapped to the output line. I then understand that a demuxer takes a single input line and based on the selector lines maps the input to one of multiple outputs. So, assuming the above is correct, my question is how does using a mux/demuxer pair to change 16 line parallel communication signal to 1 mux'ed signal, then back to a 16 parallel signal work? How would the demuxer know the selector signals to use to change the mux'ed signal back? Do you need to run the mux'ed signal line with the selector signal lines together so that the demuxer knows the proper mapping?

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  • \$\begingroup\$ Well, to start with, they contain N selector lines and 2^N inputs, not the other way around. \$\endgroup\$ – Dave Tweed May 18 '14 at 2:08
  • \$\begingroup\$ My apologies, that is what I meant. Edited my original post \$\endgroup\$ – Jarrod Christman May 18 '14 at 2:13
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There are three scenarios that I see:

  1. The selector lines would either to run with the data line (as you suggested)
  2. The selection comes from an external entity that feeds into both, the MUX and DMUX
  3. The selection lines are controlled by a synchronised entity e.g. a clock or a counter powered by a clock.
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Assume that I have an 4-bit counter at both the ends with the output lines of these counters connected to the select lines. Now what I need is a synchronous clock to do what I want.

This is called time division multiplexing (TDM) and for proper communication, the clock rate should be at least 16x times greater than the maximum signal rate.

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  • \$\begingroup\$ I accepted the other guys answer, as his covered multiple methods. Though, I thank you for an explanation of TDM, that makes a lot more sense now. Too bad I can't upvote yet, otherwise I'd upvote your answer. \$\endgroup\$ – Jarrod Christman May 18 '14 at 16:24
  • \$\begingroup\$ I don't have a problem with delayed vote. :-) \$\endgroup\$ – nidhin May 18 '14 at 16:42
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How synchronisation is achieved depends on context.

Within a board or piece of equipment counters could be reset in common and clocked together, or address lines could be used in common at both ends. In the case of shared address lines they would be able to be shared amongst multiple multiplexers.

When communications is across a serial link or encoded in a higher order data stream USB or any of the many communications protocols, a means is required to regenerate the relative timing at each end. This could be done in a substantial number of ways but they share in common the ability to identify the frame start and the values of the individual bits (usually 2 level binary but not always).


Related:

Long (long long ) ago (thesis project) I built a system which accepted a large number of analog signals (from telephone lines) and multiplexed them to a lesser number of tone detectors. This was done with standard CMOS transmission gate multiplexers (CD4051 8:1) at each end combined to make an N input x M output mux as required, where M of the N channels were gated onto the "bus" in selected time slots and output to M tone detectors. As this was all within the one piece of equipment reset signals and clocking could be distributed as required. Details grom dimmish, but it seems likely that each input channel could be assigned an address of an output tone decoder and its corresponding timeslot. A very basic sample and hold was provided on each mux output to reconstitute the signal. The common bus of this system was 'fuin'to observe on a scope. If say a single sine wave was transferred it could be seen occupying time slots in space with slots of width of 1/Mth of the total frame time. Several signals at once could be observed. With many channels in use at once the bus appeared to be 'noise' with signals being transferred end to end transparantly.

A very simple example system with a serial link can be made with eg 2 x CD4051 as mux and demux and a counter at each end. For an 8 channel system the counter can be arranged so that a high on bit 4 produces a delay in the clock signal and eg a high on the bus so that the far end sees a continuous "1"/high. This high can be used as a counter reset so that counters reset and sync. Clocking can be derived from the data signal or sent separately.

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