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I'm working with a board design that uses a Xilinx CoolRunner II CPLD (XC2C256-7VQ100I). We're currently working with the customer, and setting up the pins they'll be using external from our board to control our device. JTAG has several lines we'll use to program the CPLD on each part (TDO, TCK, TMS, TDI). In our production environment, we'd like to use several external pins to hook up to these lines to program the device. However, the end customer would like to ground these pins (Since our product will be fitting into an existing design). My question is, will there be any repercussions I need to consider about grounding those 4 pins on the device? (On the CPLD the JTAG lines are pins 45, 47, 48, 83). I'm fairly sure it shouldn't cause any issues, but haven't yet been able to find a definitive answer.

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Grounding the JTAG input lines (TCK, TMS, and TDI) is fine, although it'll make the port unusable. The JTAG output, TDO, is another matter — grounding it will cause a short circuit if it is driven high by the CPLD! If you cannot bring JTAG out to a dedicated set of pins, you're probably best off leaving it disconnected.

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  • \$\begingroup\$ Good point. It could be mitigated by putting a series resistor on the TDO line, close to the CPLD, with value chosen to ensure that the output current stays inside acceptable limits if the cold side of the resistor is grounded. There are some issues with this approach, particularly at higher JTAG speeds, but it's worth considering. \$\endgroup\$ – markt May 20 '14 at 8:31
  • \$\begingroup\$ Thanks, this answers my question. I'd vote up your response, but I'm still at 3 rep on this site : / \$\endgroup\$ – CCrew May 21 '14 at 14:44
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If unsure, you can simply add a series resistor to limit any shortage currents.

Of course, this would lead to power loss in case those JTAG pins are driven HIGH. But at least it won't blow anything up.

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  • \$\begingroup\$ We're currently in the board design stage, and don't have parts to test with physically. I'm hoping to find information on if this will be a problem specifically with possible implications of grounding JTAG lines. If you have any additional insight, I'd greatly appreciate it. I should also mention I am by no means an electrical engineer, just a programmer who happens to be the only knowledgeable person with verilog / CPLDs at my company, so if I'm just misunderstanding your answer and you could elaborate, again I'd appreciate it. \$\endgroup\$ – CCrew May 19 '14 at 14:16

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