I have an embedded system that is not cost effective to roll a custom PCB therefore my access to certain buses are limited. I had the idea of hooking my FPGA up to the unused NAND port of the system for high speed communications. I would need to write a custom driver based off the Linux MTD driver but It would allow mmap access to the FPGA.

The NAND flash peripheral clock on this specific embedded system is set at 33MHz in the Linux kernel and the SPI peripheral is 33MHz with a max clock of 30MHz. While SPI would be slower due to its serial output is their any underling complexities to the NAND bus that would make it slower than SPI?

All of my communications are 8bit commands followed by 16bit data.


1 Answer 1


The NAND interface ought to be able to operate at 2 cycle latency, and should be the limiting part in that data path. Assuming you have a 8 bit wide NAND interface, the NAND hardware ought to be faster.

You have the potential to use address and data on the NAND interface, possibly compressing command and data in a single CPU transaction (1 or 2 external accesses).

There might be other complexities that affect either port, but it should be a safe assumption that using NAND will be better for latency and bandwidth.


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