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My question is simple: Shouldn't a MOSFET keep the gate charged as long as a negative or at least zero voltage isn't applied to discharge, i.e. turn the MOSFET off?

I am trying some experiments with power MOSFETs like IRF540 and IRFP450 applying 12V between gate and source for a moment, disconnect the voltage source (the transistor is disconnected from everything) and measure the voltage between gate and source. I expected 12V in the reading but my multimeter reads 0V. Did I understand something wrong? Is this normal or are my MOSFET broken?

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If your gate-source capacitance is (say) 1nF and your multimeter input impedance is 1M ohm then you better be quick because the input impedance will discharge the 1nF in about 5*CR = 5 milli seconds.

Even if the input capacitance were 10nF and your multimeter 10Mohm, it'll discharge in about half a second.

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  • \$\begingroup\$ Yup. The gate capacitance is large enough to be a nuisance (e.g. at higher switching frequencies). But it's not large enough to keep the MOSFET turned on for any appreciable amount of time. \$\endgroup\$ – Nick Alexeev May 21 '14 at 19:43
  • \$\begingroup\$ @Andyaka That makes total sense, I should have remembered that, thank you a lot \$\endgroup\$ – rmarques May 21 '14 at 20:29
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The gate has a fixed capacitance, and your meter has a load resistance. Your meter will discharge that capacitor like an RC circuit, which means that even though the capacitor starts out charged, by the time your meter has a chance to read it will probably just show 0V. An oscilloscope would probably show the discharge curve.

Note that the gate is also extremely susceptible to static charge when it's floating like that, so just touching it with your meter could blow it unless you're using wrist straps and static mats etc.

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  • \$\begingroup\$ By blowing it you mean break it? Are you saying I can fry MOSFET just by touching them with a meter? Are they susceptible to damage only when the gate is charged or always? \$\endgroup\$ – rmarques May 21 '14 at 20:32
  • \$\begingroup\$ The Vgs limit is VERY strict. So, if you have 200V on your body (which you'd never feel as an arc) you could easily damage the part by handling it. Some MOSFETs come with a little internal protection, and generally they become less susceptible when they're built into a circuit. You can look up Human Body Model ESD and Machine Model ESD to read about the circuits people use to model the different scenarios of contact discharge. \$\endgroup\$ – Daniel May 21 '14 at 21:17
  • \$\begingroup\$ And by 'blowing it' I mean you can damage the metal oxide layer between the gate and the silicon, which will make it not work anymore. \$\endgroup\$ – Daniel May 21 '14 at 21:19
  • \$\begingroup\$ I found that Vgs limit the hard way, ending up frying 4 MOSFETs with 24V when they only could sustain 20Vgs absolute maximum... but I thought static would only be dangerous in smaller transistores, I will certainly read about that, thanks. \$\endgroup\$ – rmarques May 21 '14 at 22:40
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Related resource - too big for a comment:

Mention was made of static voltage and large transistors.
A MOSFET gate has a max allowed voltage due to the VERY thin dielectric layer between gate and channel. For a given specified voltage it does not matter if the device is small large of gi-normous - exceed Vgs max by some unknown small amount and it dieth. The gate to channel oxide ruptures and the device is usually destroyed.

A very large device MY have a larger Cgs capacitance and so save you from smaller charge discharges which are not enough to provide the charge needed to get the voltage high enough. But, generally you need vanishingly little charge compared to what is readily available to exceed Vgs max.

Generally, lower voltage (low Vds) FETs have lower Vgs max but this is not a 1:1 correspondence. Very low gate threshold voltage FETs (eg under 1V turn on) will often have Vgsmax of only 10V and some are as low as ~+ 5V but this is rare. Most FETs specify 20V Vgsmax, but this should be check on a case by case basis.

Where Vgs can exceed Vgsmax a reverse biased zener from gate to source usually provides enough protection. Where Vgate_drive exceeds Vzener the balance will be dropped across the drive to gate resistor and this needs to be designed for.

If an inductive load is used then it is VERY wise to use the Zgs zener as above to dissipate excess energy coupled into the gate from the drain circuit by Millar capacitance coupling.

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