Are there any circumstances where you would want asymetrical load capacitors on a crystal? I came across this schematic in the documentation for an NXP UART. It looks just wrong to me. Can anyone tell if this is a typo, or if there is a reason behind it?
NXP Uart Documentation (see Fig 11 on page 18).
Here's the schematic at issue:
The real question is why would you think that the two capacitors need to be the same, which implies that they serve the same purpose? Often we do see them the same. That's the coincidence you should be asking about.
There seeems to be a lot of religious beliefs and so-called "rules" out there for crystal capacitors, but none of those are substitutes for actually understanding the issues. The two capacitors serve different purposes, and you also have to consider other impedances in the circuit, not just those of the capacitors. I have discussed these issue a number of times here already. See:
https://electronics.stackexchange.com/a/17894/4512
https://electronics.stackexchange.com/a/16025/4512
I am not smart enough (yet) to summarize the information in the following links, but the information in there is pretty interesting. I have to admit, I never really thought or cared about the crystal or how it works.
http://www.crystek.com/documents/appnotes/Pierce-GateIntroduction.pdf
http://www.crystek.com/documents/appnotes/PierceGateLoadCap.pdf
According to the Atmel application note below, the unbalanced capacitor load on the crystal can make it less sensitive to noise locking it up. The downside is that it changes the duty cycle and resonant frequency of the crystal. The application note has more detail.
Atmel AVR042: AVR Hardware Design Considerations [APPLICATION NOTE]
