I'm using the LM97600RB board from Texas Instruments to capture data signals and this board contains an ADC as well as a Virtex-5 FPGA. I'm trying to add a trigger functionality to the board using an external trigger. The way the board works is that the the data is acquired by the ADC and then sent to the FPGA where it is received by GTX Transceivers and stored into internal BRAM blocks. From what I understand of how the trigger works, the data keeps being captured continuously by the ADC, but the trigger functionality would only kick in when the data is being stored. Am I right in that assumption? Maybe I need to keep checking the trigger and only when the board is triggered, I allow the data to be stored inside the internal RAM of the FPGA? Or is there an alternate way to do this?

If my thinking is right, when the the board is triggered, and the data starts being captured, I lose a few data samples due to the delay in the trigger registering and then the data being stored. How do I overcome this? Even a few nanoseconds of data is important in this case.

Appreciate any ideas on this.


I'm not familiar with your board/reference design, and you are free to implement what you see fit, so here are some general thoughts.

It sounds like the ADC-FPGA connection is via SERDES. All serializing/deserializing steps have a latency cost. The data is being serialized in the ADC and deserialized in the GTX, so there's probably a hundred nanoseconds or so of latency there; this is much larger than the FPGA's pin-to-register delay. Thus when your trigger signal hits the FPGA, there's a kind of built-in data buffer that guarantees you'll have samples starting with the trigger edge. If you care about timing on the nanosecond level, you need to look up the numbers, do the analysis, and verify in hardware.

If you didn't have latency built into the system, you could make a pipeline buffer to create your own latency. But typically the way to ensure data availability is with a ring buffer. I believe the Virtex-5 BRAMs are dual-ported, so a ring buffer should be straightforward to implement; whether you need it is up to you.

  • \$\begingroup\$ The original code for the board didn't have trigger functionality so I don't believe it has any latency built into it. So if there is that latency between the ADC-FPGA, then I wouldn't actually be losing any samples due to the delay, is that right ? \$\endgroup\$ – GamingX May 26 '14 at 16:25
  • \$\begingroup\$ Right. But you will have to figure out the exact timing. \$\endgroup\$ – mng May 28 '14 at 4:44

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