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I have a problem connecting different modules in a top module. I want to do a very simple PWM using a counter and a comparator.

Counter:

module          counter
                #(parameter N = 6)
                (
                input wire clk,
                input wire enable,
                output wire [N-1:0] q
                );
reg             [N-1:0] r_reg=0, r_next=0;


always @(posedge clk) begin
    r_reg <= r_next;
end

always @(*) begin
    if (enable)
        r_next = r_reg +1;
    else
        r_next = r_reg;
end 

assign q = r_reg;

endmodule

comparator:

module          pwm
                #(parameter N = 6)
                (
                input wire [N-1:0] cin,
                output wire pwmsig
                );

reg             [N-1:0] threshold;
reg             d = 0;

initial         threshold = 6'b011111;

always @(*) begin
    if (threshold > cin)
        d = 1'b1;
    else
        d = 1'b0;
end

assign pwmsig = ~d;

endmodule

The modules work fine and if I put everything in one module it works as intended. But if I try to connect them in a top module:

    module          top
                    #(parameter N=6)
                    (
                    input wire clk, enable,
                    output wire pwmled
                    );

    wire            [N-1:0] connection;

    counter         cnt1(
                    .clk(clk),
                    .enable(enable),
                    .q(connection)
                    );

    pwm             pwm1(
                    .cin(connection),
                    .pwmsig(pwmled)
                    );      
endmodule

I get an error message:

ERROR - Port 'clk' is unconnected. ERROR - Port 'enable' is unconnected.

RTL simulation works fine (I am only including the top module in my testbench). It just wont let me connect 'clk' and 'enable' to actual pins.

I am using Lattice Diamond 3.1.

Edit: I get the following Warnings in the Map Report:

WARNING - map: IO buffer missing for top level port ena...logic will be discarded. WARNING - map: IO buffer missing for top level port clk...logic will be discarded.

I ran the design through Quartus II and got working results... any Ideas where I am going wrong with Diamond?

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  • \$\begingroup\$ I ran your module through Xilinx XST, Map and Place and Route without problems. The 'clk' and 'enable' ports are both connected and have a load. Schematic of the synthesised circuit is here. \$\endgroup\$ – Xcodo May 23 '14 at 18:21
  • \$\begingroup\$ Your pwm does not have a clock? \$\endgroup\$ – FarhadA May 31 '14 at 1:12
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I ran into a similar issue. My problem was that I had disconnected the sub-module outputs from the main module while debugging. When the optimizer sees that the outputs aren't connected, it assumes that the module is not needed so it removes it to save space. As a result, the inputs are left floating; this will cause the errors that you are seeing.

If you want to disconnect the module at some point, assign one of the module outputs to a dummy load (like a debugging LED) and you'll be fine.

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I had this problem also with the synthesis tool Synplify pro. It turned out to be that I had inadvertently added a space in the entity port name before the tab.

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