The figure you are showing is about the prefetch of data inside the memory IC.
What you need to understand, is that even if data bus transfer rate is doubling at each generation, the internal operating frequency of the internal bus (the memory IC operating frequency) is still the same because the number of bits transfered to I/O buffer is also doubled.
The external clock frequency is the main clock of the system.
- With SDR (Single Data Rate), External clock frequency = Data bus transfer rate
- With DDR (Double Data Rate), as you are sending data on rising and falling clock edges, you are doubling the data rate, thus Data bus transfer rate = 2 x External clock frequency.
The sole evolution between SDR and DDR on your figure, is the Data bus transfer rate that is doubled using Double Data rate. But to achieve this data rate while using almost the same memory IC (at 133MHz), you need to transfer two bits to the I/O buffer (2 x 133MHz = 266 MHz)
For DDR1 to DDR2, the external clock has been doubled to double the Data bus transfer rate. But to use the same memory IC at 133 Mhz, you only to divide by 2 this external clock. But you still need the memory cell array to achieve the data bus tranfer rate by outputting 4 bits at each internal clock tick (4 x 133 MHz = 533 Mhz)
Further read : Hardware Secrets - Everything you need to know about DDR, DDR2 and DDR3 memories