# How does DDR SDRAM work? The figure is about how DDR SDRAM and DDR SDRAM2 works.

After taking some time searching, I still cannot understand the figure. Can anyone please help me understand it? In this case, is the "operating frequency of internal bus" the frequency of the whole computer system? What is the "External clock frequency"? I am so lost.

The figure you are showing is about the prefetch of data inside the memory IC.

What you need to understand, is that even if data bus transfer rate is doubling at each generation, the internal operating frequency of the internal bus (the memory IC operating frequency) is still the same because the number of bits transfered to I/O buffer is also doubled.

The external clock frequency is the main clock of the system.

• With SDR (Single Data Rate), External clock frequency = Data bus transfer rate
• With DDR (Double Data Rate), as you are sending data on rising and falling clock edges, you are doubling the data rate, thus Data bus transfer rate = 2 x External clock frequency.

The sole evolution between SDR and DDR on your figure, is the Data bus transfer rate that is doubled using Double Data rate. But to achieve this data rate while using almost the same memory IC (at 133MHz), you need to transfer two bits to the I/O buffer (2 x 133MHz = 266 MHz)

For DDR1 to DDR2, the external clock has been doubled to double the Data bus transfer rate. But to use the same memory IC at 133 Mhz, you only to divide by 2 this external clock. But you still need the memory cell array to achieve the data bus tranfer rate by outputting 4 bits at each internal clock tick (4 x 133 MHz = 533 Mhz)

• There is one more thing I need to ask. Can I say that the "external clock frequency" is the same as the bus frequency ? So if that is the case, then DDR2 is better than DDR1 in the sense that it can double the bus frequency => this eventually doubles the data bus transfer rate. And also what is the "clock cycle" in the figure ? Is it the clock cycle of the "external clock" ? May 25, 2014 at 10:05
• I think the "clock cycle" mentioned in the figure is related to the "internal bus". But I am not sure. May 25, 2014 at 10:11
• You only have one main clock source for both ends : external clock frequency. This frequency will be divided for the memory chip and for the external bus you keep the same frequency but double the bandwidth by using DDR. The clock cycle is related to the clock of the corresponding bus : on the left it will be 133MHz, and on the right side 2x external clock frequency (because of DDR, it says 1/2 clock cycle)
– zeqL
May 25, 2014 at 21:37

I'm going to take a shot at this, but I don't personally understand the guts of DDR RAM.

"Operating frequency of internal bus" refers to the internal bus of the RAM module.

"External clock frequency" is the frequency of the RAM, in its connection to the processor.

"Data bus transfer rate" in the DDR cases is 2x the External Clock Frequency because data is transferred on each transition (both up and down) of the clock instead of the more traditional once-per-cycle.