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I have designed a circuit in System Generator. I want to put a FIFO at the output before out gateway as shown in the below picture

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When I run it I face to the following error

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I should connect the we and re pins to a clock, hence I set clock probe at their inputs. I do not know where is wrong. Can any one help me in driving these two input ports of FIFO?

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  • \$\begingroup\$ Why exactly are you adding the FIFO to this design? This will dictate how you connect its various control lines. \$\endgroup\$ – Dave Tweed♦ May 24 '14 at 21:30
  • \$\begingroup\$ @DaveTweed I need to reed the output via UART and RS232. their bit rate is so low, so I need to save the data and read it with suitable spead \$\endgroup\$ – CLAUDE May 24 '14 at 21:33
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    \$\begingroup\$ In that case, you need a signal from the "Subsystem CPM1" block that becomes the WE for the FIFO, and a signal from the UART that asserts RE whenever the FIFO is not empty and the UART is ready to accept a new byte. Unfortunately, I really don't know the details of how this gets done in System Generator. \$\endgroup\$ – Dave Tweed♦ May 24 '14 at 23:41
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You are geting the error because you can't connect clock probe to a system generator block. But appart of that, what you are doing in this scheme, is the same of getting the WE and RE connected to '1' ! If your idea is connect 2 different clock domains, this is done with the clock signal inputs, that dont appear in sysgen blocks on simulink. But you can simulate this with constants in WE and RE, with diferent Rates.

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