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I am coding a display control for the Spartan 3E. It has 8 LEDs. When the ALU's state signal (from other block) is "00" the MSBs and LSBs are time-multiplexed for one second each byte. When state is not "00" then a LED is rotated to right every 125 ms. The FPGA clock is 100 MHz. I have the following code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity display_control is

  port (
    clk        : in  std_logic;
    rst        : in  std_logic;
    state      : in  std_logic_vector(1 downto 0);
    MSB_result : in  std_logic_vector(7 downto 0);
    LSB_result : in  std_logic_vector(7 downto 0);
    leds       : out std_logic_vector(7 downto 0));

end display_control;

architecture rtl of display_control is
  signal en_1Hz                    : std_logic; 
  signal en_8Hz                    : std_logic; 
  signal cnt0_next, cnt0_reg       : integer;
  signal cnt1_next, cnt1_reg       : integer;
  signal ror_next, ror_reg, x      : std_logic_vector(7 downto 0);
  signal muxctrl_reg, muxctrl_next : std_logic;

  constant PRESCALER0_DIV_FACTOR : integer := 100;  --000000;  -- 100M = (100MHz/0.5MHz)
  constant PRESCALER1_DIV_FACTOR : integer := 12;  --500000;  -- 12.5M = (100MHz/8MHz)

begin

  -- registers
  process (clk, rst, en_8Hz, en_1Hz)
  begin
    if rst = '1' then
      cnt0_reg    <= 0;
      cnt1_reg    <= 0;
      muxctrl_reg <= '0';
      ror_reg     <= (others => '0');
    elsif clk'event and clk = '1' then
      cnt0_reg <= cnt0_next;
      cnt1_reg <= cnt1_next;
      if en_1Hz = '1' then
        muxctrl_reg <= muxctrl_next;
      end if;
      if en_8Hz = '1' then
        ror_reg <= ror_next;
      end if;
    end if;
  end process;

  -- register's next state
  cnt0_next    <= cnt0_reg +1 when cnt0_reg /= PRESCALER0_DIV_FACTOR -1 else 0;
  cnt1_next    <= cnt1_reg +1 when cnt1_reg /= PRESCALER1_DIV_FACTOR -1 else 0;
  muxctrl_next <= not muxctrl_reg;
  ror_next     <= ror_reg(0) & ror_reg(6 downto 0);
  -- prescalers output
  en_1Hz       <= '1'         when cnt0_reg = PRESCALER0_DIV_FACTOR -1  else '0';
  en_8Hz       <= '1'         when cnt1_reg = PRESCALER1_DIV_FACTOR -1  else '0';

  -- output logic
  x <= LSB_result when  muxctrl_reg = '0' else MSB_result;
  leds <= x when state = "00" else ror_reg;

end rtl;

But when I synthesize the code I obtain the following warnings:

WARNING:Xst:3002 - This design contains one or more registers/latches that are directly
   incompatible with the Spartan6 architecture. The two primary causes of this is
   either a register or latch described with both an asynchronous set and
   asynchronous reset, or a register or latch described with an asynchronous
   set or reset which however has an initialization value of the opposite 
   polarity (i.e. asynchronous reset with an initialization value of 1).

and

WARNING:Xst:1426 - The value init of the FF/Latch cnt0_reg_31_LD hinder the constant cleaning in the block display_control.
   You should achieve better results by setting this init to 0.

How can I fix it?

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  • \$\begingroup\$ You should not combine clocked and combinatorial process in one. Even thought the tool accept this, it is not the right coding style. You should split your process into 2 separate process, one with (clk, rst) in the sensitivity list, and the second one with (en_8Hz, en_1Hz) in it. \$\endgroup\$ – FarhadA May 27 '14 at 7:49
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If I'm understanding the second warning correctly, ISE would like you to give an explicit start value to some of your signals:

signal cnt0_next, cnt0_reg : integer := 0;
signal cnt1_next, cnt1_reg : integer := 0;
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