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If the processors are working with 64bits, then why do they need Bus protocols to be as high as 1024bits.

Is it for re usability?

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The internal ALU width of a CPU might be 32 or 64 bits, and this represents the amount of data that can be processed per CPU clock cycle. On a modern processor, the CPU(s) are running at clock speeds of several GHz. If each operation involves 1-2 input operands and a result, this represents a raw data bandwdith of tens of GB per second.

Processor chips have internal memories, called caches — often in several levels, that handle much of that raw processor bandwidth, taking advantage of the fact that data tends to be reused. Caches are used as buffers for the contents of external memory, and so data frequently needs to be transported between the caches and the external memory.

The external memory interface runs at a much slower rate than the processor core, usually by a factor of about 10 (i.e., hundreds of MHz). In order to have as much bandwidth as possible over this interface, burst transfers are used to transfer entire cache "lines" at a time. Since the ability to adderess individual words within an external transfer is not important, it makes sense to make the data bus as wide as practical in order to minimize the number of clock cycles required to complete a burst transfer.

An external bus of 1024 bits (128 bytes) will be able to transfer 1kB of data in 4 clock cycles (DDR). If the bus is running at, say 500 MHz, this represents a raw bandwidth of 128 GB/s, which makes it a good match for a multi-core processor.

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  • \$\begingroup\$ It might be worthwhile to clarify the concept of spatial locality. ("that data tends to be reused" is temporal locality, but larger cache lines exploit spatial locality) Also, "make the data bus as wide as practical" is somewhat constrained by cache line size and DRAM burst length not just cost/physical limits. \$\endgroup\$ – Paul A. Clayton May 27 '14 at 16:15
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A typical processor can execute hundreds of instructions in the time required for a typical DRAM ("bulk" memory chip) to fetch a single piece of data. If every piece of data required by the processor had to be fetched separately from RAM, even today's fastest processors would be little better than those of ten years ago. In many cases where a processor wants a piece of data, however, it will also want other data that's nearby. In a modern system, when the processor requests a piece of data that needs to be fetched from slow memory, the memory subsystem won't just fetch enough data to satisfy the request, but will instead copy into faster RAM a large chunk of data which contains the requested piece. If the request is followed reasonably soon by requests for any of the other data in that large chunk, the requests can be satisfied using the high-speed RAM rather than the slower main memory.

Note that faster RAM is much more expensive than bulk DRAM. While it might be possible to build a system with many gigs of extremely fast memory, the added performance would in most cases be insufficient to justify the cost compared with a system that combines a large amount of slower main RAM with smaller sections of faster memory. For operations which require processing large amounts of sequential data, increasing the size of chunk that can be read in each transaction will reduce the number of separate transactions required. Because not all memory operations are sequential, doubling the transaction size won't cut the number of transactions in half, but system designers have apparently determined that expanding the chunk size from 512 bits to 1024 bits offered a sufficient performance increase to justify the cost.

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To get a high bandwidth (number of bits transferred per second).

Roughly the situation is:

  • the consumer needs 64-bit chunks of data very fast.

  • the producer can produce data, but much slower.

  • solution: use 16 produces, that each produce 64 bits (at a slow pace), 1024 bits in total. Buffer these bits.

  • the consumer consumes from the buffer. If all goes well it consumes the entire buffer in the time that the producers can produce one new buffer worth of data, and everybody is happy.

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