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I plan to use KC5032A40 as a clock source for CoolRunnerXPLA3 256. I power it with 3.3V and interface it as suggested:

enter image description here

I perform the measurement at the Test Point and do not add any CL capacitance, the probe is set to 10x. Instead of getting theoretical 0V and 3.3V swings, I see -1V to 4V swings:

enter image description here

Questions:

  1. Is this a correct measurement? Will the oscillator provide proper voltage swings with some load on the output?

  2. Is this a reasonable choice for my application? Any suggestions for oscillator choice to drive CPLD?

  3. Is it a proper practice to connect the oscillator to any IO pin, or it should be connected to the one of the special CLK0:4 pins (table 4 of the manual)? What's the purpose of such pin as IN0/CLK0?

  4. Could I also use such oscillator as an external clock for a microcontroller instead of XTAL oscillator?

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  • \$\begingroup\$ I think this swing is because there is no load connected to the output except the oscilloscope. The input impedance of the oscilloscope is so high so there is no matching between source and load impedance which causes reflections on that clock which appear as overshoots and undershoots causing this swing to occur. \$\endgroup\$
    – Abdella
    May 27, 2014 at 22:56
  • \$\begingroup\$ Also, what oscilloscope are you using? What's the bandwidth of the probe at 10x ? \$\endgroup\$
    – Abdella
    May 27, 2014 at 23:21
  • \$\begingroup\$ @Abdella Thank you for the pin-clocks advice. That's the Rigol DS1102E and it says 100MHz, 1GS/s. But, I wish I was more advanced user of my oscilloscope to tell you what's the bandwidth at 10x. \$\endgroup\$
    – Nazar
    May 28, 2014 at 14:15
  • \$\begingroup\$ 1x and 10x probe specs should be written on the probe itself, at the BNC connector side. \$\endgroup\$
    – Abdella
    May 28, 2014 at 15:37

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I use these osc modules for microcontrollers and EPLDs no problem. The over-voltage you are seeing is more than likely a "feature" of your scope probe. I get it on my Tektronix scope and I'm just "used to it"!!

For CPLD/EPLD/FPGAs there are dedicated pins for the master oscillator but if it isn't the master oscillator then no problem, connect it to any IO pin.

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  • \$\begingroup\$ That's going to be one and only clock provided to the CPLD. Would it still matter to which pin the osc should be connected? \$\endgroup\$
    – Nazar
    May 27, 2014 at 20:24
  • \$\begingroup\$ CPLDs, and correct me someone if I'm wrong, have dedicated master clock lines. I'm not saying you can't use others but everyone I've used (Altera EPLDs and an FPGA) had dedicated clk pins. \$\endgroup\$
    – Andy aka
    May 27, 2014 at 20:26
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    \$\begingroup\$ The CPLD you are using has 4 global clock pins which are optimized for clock inputs. It's better to use one of them to reduce the delays introduced by the internal routing of the CPLD. \$\endgroup\$
    – Abdella
    May 27, 2014 at 23:31

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