To be synthesisable,
reg types can only be assigned within one
always block. Verilog allows
regs to be assigned anywhere for test bench and non-synthesiable modeling purposes.
repeat is a non-synthesiable keyword. Again, it is for test benches and non-synthesiable modeling.
always @ (count) block is inferring latching logic for two reasons:
- The sensitivity list is incomplete. It should be
always @ (count or res) or
csx,dcx,wrx,rdx,d_out are not assigned in every branched condition, this infers latches.
Most likely you want to put in one always block and have
csx,dcx,wrx,rdx,d_out be flops:
always @(posedge clk or posedge res) // clock edge or async reset
if (rst == 1'b1) begin // reset
// assign all regs a constant default value
csx <= 1'b1; // use non-blocking assignment (<=)
wrx <= 1'b0; // recommenced to use to use explicit bit-width and radix
// ... other conditions
count <= count + 1'd1;
If your simulator and synthesizer support SystemVerilog, I'd recommend using the
always_ff (for flip-flops),
always_comb (for combination logic) and
always_latch (for intended latches). They are like the traditional
always expect they throw compiling errors if more than one
always* block is assigning the same register, if blocking delay elements are found withing the block, and additional checks for synthesisablity. It also give improved guidance to linting and logical equivalency checking tools. It will give the same result as properly coded Verilog.