I want to move the low side enable switch of my H-bridge onto the high side, because for safety reasons it's better to turn off the tap than plug the drain. I'm powering a 24V, 35W BLDC, so it's nothing too serious. Rather than adding a 36V supply to my board only to drive a high side NFET, I decided to go with a PFET, however its logic is inverted, and I want the H bridge to turn off in the event the enable line de-energizes. That way, it fails safely.

This is the design I came up with:

enter image description here

The transistor is by default off unless an enable signal is applied to Q2. If Enable should droop or get disconnected, the H bridge will be disabled.

The issue is that since the H-bridge will be on most of the time, there will be a current through R1 to ground. Since I don't want to waste my battery, is there any way I can pick a large R1 to minimize that current, without trashing the gate drive of Q1?

  • 1
    \$\begingroup\$ The answer will depend on how fast you want to turn off the H bridge, and what +24V is doing. You won't want to apply full 24V gate to source of Q1. And while you're at it add a pull down resistor gate to source of Q2, in case EN goes tri-state. \$\endgroup\$
    – gsills
    May 29, 2014 at 20:14
  • \$\begingroup\$ Perhaps you should include a reference to a data sheet for your H-bridge or include it in your schematic if it is a discreet circuit. If possible, it would seem more logical and efficient to include gating of the high-side drivers within the H-bridge instead of switching the power externally. \$\endgroup\$
    – Tut
    May 29, 2014 at 20:40
  • 2
    \$\begingroup\$ You should add a pull-down resistor to EN if you want it to do anything predictable when disconnected. \$\endgroup\$ May 29, 2014 at 21:54
  • \$\begingroup\$ the above is a condensed version of another schematic which isn't necessary to post in full. \$\endgroup\$
    – BB ON
    May 30, 2014 at 14:40

2 Answers 2


One way would be to add a CMOS buffer driving stage. If you have small but high voltage transistors/mosfets in an inverter setup driving the main PMOS, there will be virtually no ON or OFF current, only transition current. The buffer cmos transistors will have a much smaller gate area than your main PMOS and therefore won't take nearly as much current to turn on and off. In that way, you'll be able to use a much larger driving resistor for the input stage while still achieving the same performance.

The setup should be something like this:


simulate this circuit – Schematic created using CircuitLab

The reason for two cmos inverters is to maintain the state of input low = output off rather than input low = output high.

The Zener's are added to prevent the Vgs's of the MOS's from getting too high.

Alternately, you could just add a Zener. It would eliminate the high voltage on the PMOS gate source voltage. When the input is high, you'll get a significant reduction in current because you'll only have (Vdd-Vzener)/R rather than Vdd/R. This will be balanced with the reduction in voltage swing you need to turn on/off the PMOS.


simulate this circuit

  • \$\begingroup\$ In your top circuit, what limits the current in the second zener? Also in that circuit, note that there are likely to be large current spikes during the transitions from the lower MOSFET turning on and the upper one turning off since this will not occur at the same gate voltage. \$\endgroup\$
    – Tut
    May 29, 2014 at 22:10
  • \$\begingroup\$ @Tut Good point. I've added a current limiting resistor. \$\endgroup\$
    – horta
    May 30, 2014 at 2:51

Q1, in your diagram is in danger of frying because you will be applying the full 24V to the gate and making smoke. Ideally you would have a resistor in the drain of the N channel MOSFET so that it forms a potential divider with R1 and restricts the gate-source voltage to maybe -15V i.e. a value that won't damage the P ch MOSFET.

How quick to turn on and turn off with a 10k resistance for R1 and the extra R I mentioned?

If the P ch FET has a 10nF gate capacitance and the driving impedance is 10kohm then the CR time is going to be 100 \$\mu\$s and there will be about 5 CR times to fully turn on and turn off the P ch FET. So, reckon on 0.5 ms.

Is 10k too small? If so then maybe a different approach is needed but given that the motors are 35 watt I tend to think 10k will be just fine.


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