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Can anybody help with the circuit and specifically the selection of values for \$R_1\$ and \$C_1\$?

Schematic I tried to create a p-channel based MOSFET 1A switch for MCU based upon OnSemi AND9093 Using MOSFETS in Load Switch Applications.

After reading the application note the following choices were made:

  • \$R_1\$ is 5 \$k\Omega\$ to limit current through Q1 to ~1mA at +5VDC
  • \$R_3\$ is 5 \$k\Omega\$ sized for ~1mA through the GPIO pin of MCU
  • \$R_4\$ is 50 \$k\Omega\$ to drain any voltage between GPIO pin of the MCU, when MCU is not yet initialized to prevent accidental switching on.
  • \$R_4\$ is 50 \$k\Omega\$ based upon 10 times the value of \$R_3\$.

The application note also refers to the need for \$R_1\$ and \$C_1\$ to limit the inrush current due to the capacitance of the load. Thats where I got stuck. The formula (eq. 8) on page 4 is

\$R_1 = R_2\cfrac{(V_{in} - V_{sg(max)})}{V_{sg(max)}}\$

where

  • \$V_{in}\$ = +5V
  • \$R_2\$ = 5000 \$\Omega\$
  • \$V_{sg(max)}\$ of IRF7406 (\$Q_2\$) =[Gate-To-Source Voltage] = \$\pm\$20V (Did I read the data sheet correctly?)

It looks like using the negative value for \$V_{sg}\$ does not make sense as it would result in negative \$R\$. Is that correct?

The calculation is then

\$R_1 = \cfrac{5000 (5 + 20)}{20} = 6250 \Omega\$

The formula for \$C_1\$ (eq.9) is on page 4. I estimate \$C_{load}\$ as 20\$\mu\$F and \$I_{inrush}\$ at 5A. Are assumptions valid? Regular load will be \$I_{load} = 0.5A\$

Then I calculate \$C_1\$ as 0.001716\$\mu\$F. Does the value for \$C_1\$ make sense?

I plan to use the circuit for 12V in another incarnation, so I am trying to understand the calculations.

IRLML6346TRPBF is selected for lower Rds compared to 2N7002 for example.

P.S. I am an amateur DYI trying to do simple things.

Here's the updated schematic without D2:

enter image description here

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After reading the application note the following choices were made: •R1 is 5K to limit current through Q1 to ~1ma at +5VDC

No, that will be done by the total of R1 and R2. And why limit the current to 1 mA?

•R3 is 5K sized for ~1ma through the GPIO pin of MCU

No, you can use pretty much any size resistor you want, since the gate resistance of a MOSFET is very large. Admittedly, you want some resistance to reduce the peak current into the gate capacitance (270 pf) but it doesn't need that much.

•R4 is 50K to drain any voltage between GPIO pin of the MCU, when MCU is not yet initialized to prevent accidental switching on.

•R4 is 50K based upon 10 times the value of R3.

While this is a good general practice, in the present case it doesn't much matter, since the MCU pin will incorporated active pull-down. That said, you might as well, and your choice of ratio is correct.

The application note also refers for the need for R1 and C1 to limit the inrush current due to the capacitance of the load. That were I got stuck. The formula (eq. 8) on page 4 is

R1 = R2 *( Vin - Vsg(max))/Vsg(max)

where •Vin = +5V •R2 = 5000 •Vsg(max) of IRF7406 (Q2) =[Gate-To-Source Voltage] = +/-20V (Do I read the datasheet correctly?)

It looks like using the negative value for Vsg does not make sence as it would result in negative R. Is that correct?

You're missing the point. Setting the ratio of R1:R2 is intended to keep from exceeding the limit on Vsg when the supply voltage is greater than Vsg. In this case, since Vin (5 volts) is less than Vsg(max) (20 volts), that can't happen, and what you have to worry about is producing a Vsg which is too small and does not turn on Q2. In the current case, your values of R1 and R2 will produce a gate drive of 2.2 volts, which seems low.

The calculation is then

R1= 5000 * (5 + 20) / 20 = 6250

In this case, I'd suggest using R2 = 4k, and R1 = 1k, to give a nominal 4 volt Vsg drive.

The formula for C1 (eq.9) is on page 4. I guessestimate Cload as 20uF and Iinrush at 5A. Are assumptions valid? Regular load will be Iload=0.5A

I've no idea.

Then I calculate C1 as 0.001716uF. Does the value for C1 make sense?

More or less. Go back and redo with a new R1.

I plan to use curcuit for 12V in another incarnation, so I try to understand the calculations.

Note that, even with a 12 volt supply, you can't exceed Vsg(max) no matter how hard you try.

IRLML6346TRPBF is selected for lower Rds compared to 2N7002 for example.

Why? You've already stated your intent to limit Q1s current to 1 mA. Even if Rds is 1 ohm, you'll only have a voltage drop of 1 mV. You're using a 3 amp MOSFET to pull 1 mA.

And finally, what in the world is D2 doing? You do realize that that's a 25 volt zener in a 5 volt circuit?

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  • \$\begingroup\$ About D2, maybe with an inductive load a turn off voltage spike could damage Q2 gate through C1, so tha spike is clamped via D2. The strange thing is that Q2 already has the protection diode, as every power mosfet. \$\endgroup\$ – Vladimir Cravero May 31 '14 at 9:27
  • \$\begingroup\$ @VladimirCravero - For a negative load spike, D1 already has that covered. For a positive spike, D2 will be forward biased, and no zener action occurs. \$\endgroup\$ – WhatRoughBeast May 31 '14 at 11:20
  • \$\begingroup\$ Maybe he wanted to use a Schotky... \$\endgroup\$ – Vladimir Cravero May 31 '14 at 11:34
  • \$\begingroup\$ @Vladimir Cravero: D1 was placed as the thinking was to be able to power both SSR and a regular relay. The latter is inductive. \$\endgroup\$ – sdo_riga May 31 '14 at 11:58
  • \$\begingroup\$ I know what D1 is there for, the question is: what about D2? \$\endgroup\$ – Vladimir Cravero May 31 '14 at 12:17

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