# In a JK Binary Counter from 0 to 9, why is the NAND gate connected to the second and fourth J-K flip flop and not the first and fourth?

In a binary counter design using 4 J-K flip-flops, that counts from 0 to 9, the flip flops are reset when the output from the 2nd flip flop NAND the 4th flipflop equals to 0. Since binary 9 is 1001, why is the NAND connected to these 2 outputs and not the first and fourth since it's the first and fourth bits that are 1s. • If you connected it to the first and fourth, you'd have a 0-8 counter. – Connor Wolf May 31 '14 at 12:08

The circuit you cited is a ripple counter, not a synchronous counter. It actually has eleven states, 0000 through 1010, but as soon as the last state is reached, the NAND gate immediately (asychronously) resets the flip-flops to the 0000 state.

In a synchronous counter, all of the flip-flops would share a common clock, and you'd control the sequence of states by driving their J and K inputs. This would require a few additional gates, which would include decoding the 1001 state so that the counter goes directly to the 0000 state on the next clock edge.

That's because you want to reset the FF when the output would be 1010, i.e. 10. When both bits are one, and that only occurs when the output is 10 if you stay in the 0..9 range, the NAND output goes low and pulls low all the negative reset inputs of the FFs, resetting your counter.

When you want to design a counter which counts 0000-1001 (0 to 9), You have to reset when it reaches 1010 (10).

If you reset it when it is 9 (1001), then you wont be able to see the count 9 ( of course there will be a glitch of 9 but it will stay only for a very small time )

So when you reset when it reaches at 1010 (10) - It will actually show 1010 (10), but only for a very small duration (Practically you can not see it).

Since you are using 4 flip flops, it is a mod 16 counter : it counts from 0000 to 1111 and then recycles to 0000. However, presence of NAND gate changes situations. If you look carefully, the CLR inputs have bubbles attached. This means they are active low inputs. In other words, for flip flop to clear, the input to the CLR input must be LOW. Now, a low input can be produced by NAND gate only when both of its inputs are 1. Since the NAND gate is connected to 2 and 4 flip flops, this happens for combination 1010 which is binary 10. So the counter will recycle at state 10.

Hope i am correct. (Note that for a counter to count from 0-9, it must recycle at 10)