I am playing around with some SAR (Successive Approximation) A/D-converters. I have made a test circuit where I have a 16-bit DAC from Texas Instruments (R2R-based) and an 16-bit SAR ADC from Analog Devices. Using a micro controller and some SPI programming, I am able to output a voltage on the DAC and sample it with the ADC. The goal of this test is to verify that the resulting data is a straight line, with some noise.

I let the DAC settle for at least 10 times the required settle time and the output is low-pass filtered to get rid of noise. Although I could sample quite fast, I need some time to transfer data from the micro controller to the PC, so I only make roughly 2-3 samples each second. I make sure that the ADC conversion is finished before latching a new voltage on the DAC.

After about 4000 samples regularly spaced over the entire full scale range, the result can be plotted with the DAC 16-bit word (X) and the ADC (Y). The result looks strange and If I zoom in, there is some kind of periodic "noise" (look at the plot below).

Samples from SAR ADC

I can definitely say that there is no such signal problems when measuring with my scope. There is some noise but that is like 10 mV amplitude. So something is wrong here. I also measured my voltage reference and supply lines and there are no noisy problems here either. I would accept the result if the "spikes" were like 1-10 LSB and random but this is on a much bigger scale and somewhat periodic. The periodicity could be a sign of very low resolution sampling of a linear changing signal but this is not the case. I think this is too large to be quantisation noise. The plot below shows the full range version. The problem is so big that it can be clearly seen in this plot as well. The DAC and ADC is not using the same full scale voltage which explains the flat areas in both ends of the scale.

Full range of samples

Keep in mind that the plot shows maybe about 50-100 samples with only a few samples per second, so we are talking about very slow sampling of a DC voltage that only changes after the ADC conversion is done. The voltage reference is filtered and so is the input signal to the ADC.

I have done the same with a 18-bit SAR ADC as well. Same problems.

  • \$\begingroup\$ It looks like you have a stuck bit somewhere in the digital path. Since you get the same results with two different ADCs, check the connections to the DAC carefully. \$\endgroup\$
    – Dave Tweed
    May 31, 2014 at 13:55
  • \$\begingroup\$ What @DaveTweed said. The bumps are suspiciously binary looking. In particular check your SPI mode and timing for the DAC carefully. If, for example, you're clocking off the wrong edge it might 'almost' work. \$\endgroup\$ May 31, 2014 at 13:57
  • \$\begingroup\$ Thanks. I am beginning to think that it is not the analog circuit but more like a SPI-problem or something else digital. The Y-scale should go from -32768 to 32767. Or in this case where the Two's complement is converted to offset binary, 0 to 65535. It does not in my plots. So something is definitely wrong. \$\endgroup\$
    – pvh1987
    May 31, 2014 at 14:16
  • \$\begingroup\$ Just to check the obvious, does the ADC have all the right capacitance, a good ground plane, no digital lines under the chip, and separate analogue and digital power supplies? \$\endgroup\$ May 31, 2014 at 20:59

1 Answer 1


OK - I solved the problem. In my SPI setup for the microcontroller, I changed both the clock polarity and the clock phase and it solved the problem. I now have very clean, smooth curves.

I makes sense now. The 16-bit words read out from the ADC were indeed not correct and contained both information from the previous word and the current. That explains both the periodicity and weirdness in the plots.

Thankfully both the DAC and ADC seems to work fine with the new clock and phase polarity, despite being from different manufactures :-)

  • \$\begingroup\$ Do you think that SPI works better in noisy environments than I2C devices? \$\endgroup\$
    – bardulia
    Aug 28 at 20:14

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